added a note to specify that tc2 has been deprecated
Change-Id: I7ab69a2560e0e56379f4e144d41da20671c1ca9d
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Increase BL31 size to have room to spare for debugging with EL3 SPMC.
Change-Id: I6e260a284ed2aa5d515b45be90ee2cdeded9c6a9
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
With PLAT=qemu, the EL3-SPMC data store is provided as an array of
uint8_t and implicitly with a 1 byte alignment. But the way the data
store is used it must have a larger alignment, so change to double-word
alignment for maximum compatibility.
Change-Id: I4e9b901889078fee4b87f8333257bdc076386572
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Currently when building with PLAT=qemu SPD=spmd SPMC_AT_EL3=1
SPMD_SPM_AT_SEL2=0, there is a build error since
plat_spmd_handle_group0_interrupt() is called irrespective of
SPMC_AT_EL3. Fix this by making plat_spmd_handle_group0_interrupt()
available if SPD_spmd is defined only.
Change-Id: If5f650d2bd3675cbb4b509e9e3743d3865d7c812
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
* changes:
docs(changelog): add some architecture features
docs(changelog): create SPD scopes
docs(changelog): update some scope for release note
docs(changelog): add subsections for STM32MP25
The name field of console_info structure was missed
in checksum calculation. This is corrected by adding
a new helper checksum_calc() which computes the
checksum in a field agnostic manner.
Change-Id: I5c39ee43f1fa20872c37846e3feeabd0525a47ae
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
This small change removes the footnote from Poetry that it is only used
for building documentation, as it is now used for some of the Python
tooling in the repository from the build system.
Additionally, add a link to the official installation guide for Poetry.
Change-Id: Ie36b7ecd8066cbf2a14a1085d84fa9bd9c4409ba
Signed-off-by: Chris Kay <chris.kay@arm.com>
* This patch adds some details on the EL3/Root-Context
and its related interfaces.
* Additionally it updates the existing details on the
interfaces, related to various CPU context entries which
have been improvised recently.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I81a992fe09feca4dc3d579a48e54a4763425e052
To ease release note preparation, add some missing scope in the
changelog.yaml file.
Change-Id: I9426cf7b90455a487c4653c3fc9a6a718c13df7b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The STM32MP2 family has 3 different types of SoCs (STM32MP25, STM32MP23
and STM32MP21). For the moment only STM32MP25 is partly supported in
TF-A. Add a dedicated subsections for STM32MP25. The other ones will be
added later. The same is done for FDTS scope.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ia18824a7b649bcd1ffa631e3aa0ecb3fd0b2d038
Use TOOL_ADD_IMG_PAYLOAD instead of TOOL_ADD_IMG to generate the BL31
device tree blob to be included in FIP. This allows building all TF-A
binaries and FIP in a single command. Else, as TOOL_ADD_IMG evaluate
the existence of the file before building it, we have a build error.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I72d2f70733c49792d0321ad07f5a3bbd283a36d4
The timer is required when setting console. In BL2 the timer init is
done in clock driver init. This is not the case in BL31. So initialize
the generic_delay_timer_init() just after stm32mp2_clk_init() call.
This is required after the recent changes in timer framework [1].
[1]: a6485b2b3b refactor(delay-timer): add timer callback functions
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4e84a45fc526ed132e97b238596aa69ddfc2b058
In order for directories to be automatically created when used as a
dependency, they must end with a forward slash (`/`). This is because we
have a pattern rule (`%/`) to create a directory anywhere where a
directory is required as a direct dependency.
Change-Id: Ib632d59da0745f6cadb0a839a62360aeca25c178
Signed-off-by: Chris Kay <chris.kay@arm.com>
Change the interrupt name "combined-mbx" to "combined", which is the
correct naming defined in the mainline kernel.
Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: I8d2da2dd0e9dac2bed3963efc695a277bb5e14bd
Make this function return values from crypto_ret_value.
The previous method of returning the mbedtls error code
on failure meant that the authentication module couldn't
correctly parse failures from this function.
Change-Id: I9fe6eba1fc79e8f81004f8cd202781aea907e963
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
The TF_FLAGS variable must be recursively expanded as the rules that use
it are defined before it has been fully defined. That has the
unfortunate side effect of spawning a subshell that calls the compiler
for every file that is being built, thrashing multicore build times.
We don't cater to the possibility of the toolchain changing mid build so
precomputing this value would be more sensible. Doing a clean build on
an Intel dual socket Xeon Gold 5218 (i.e. 64 threads) workstation used
to take about 9 seconds. After this patch it takes about 1.5. Single
core performance went from ~45 seconds to about 25.
Change-Id: If56ed0ab3cc42bc482d9dd05a41ffbff4dd7f147
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Most of the macros in build_macros.mk get lazily evaluated. That's
mostly fine, except for the fact that the `uppercase` macro needs to
spawn a subshell to get its output. And the target for every file
requires calling `uppercase` many, MANY, times, thrashing performance on
even the most trivial of make commands.
We can be a little clever and only call `uppercase` a handful of times
and then pass around the already uppercased strings.
The same is true about the verbosity augmentation variables. Simply
changing them to simply expanded variables allows for them to be
pre-processed and then used over and over again.
`make realclean` is a pretty good benchmark for this as it doesn't do
much else but must process all the rules, like every other make command.
On a clean checkout of TF-A on an Intel Xeon Gold 5218 (i.e. slow
single-core) workstation, that command used to take about 7 seconds.
With this patch it takes about 0.5.
Change-Id: I632236a12a40f169e834974ecbc73ff80aac3462
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
* This patch adds support to tsp (BL32) Image, to exercise
EL1_context registers at S-EL1.
* Adds a SMC function ID "MODIFY_EL1_CTX" to handle EL1_CTX
registers at S-EL1 and overwrite them.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Id4f2b3b748f7bc9e6c9d72a2f03d50aefbfb61cb
Correct feature list assignment to apply ARM v8.7 features
to `armv8-8-a-feats` instead of `armv8-7-a-feats` for ARM v8.8
compliance.
This was highlighted during the build of TC4 with ARM_ARCH_MAJOR=8
and ARM_ARCH_MINOR=8.
Change-Id: I6c48a3ffa2f1e18d5e4a6484a823c9112dddd751
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The buffer size allocated for the raw ECDSA signatures
was too small for P-384 signatures. This led to mbedtls
aborting the generation of the raw sig.
Fix this by increasing the buffer size to the required
value.
Change-Id: I06a9cfe1f4cb2603c5fbe945714e90460c24edb8
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Armv8.6 introduced the FEAT_LS64 extension, which provides a 64 *byte*
store instruction. A related instruction is ST64BV0, which will replace
the lowest 32 bits of the data with a value taken from the ACCDATA_EL1
system register (so that EL0 cannot alter them).
Using that ST64BV0 instruction and accessing the ACCDATA_EL1 system
register is guarded by two SCR_EL3 bits, which we should set to avoid a
trap into EL3, when lower ELs use one of those.
Add the required bits and pieces to make this feature usable:
- Add the ENABLE_FEAT_LS64_ACCDATA build option (defaulting to 0).
- Add the CPUID and SCR_EL3 bit definitions associated with FEAT_LS64.
- Add a feature check to check for the existing four variants of the
LS64 feature and detect future extensions.
- Add code to save and restore the ACCDATA_EL1 register on
secure/non-secure context switches.
- Enable the feature with runtime detection for FVP and Arm FPGA.
Please note that the *basic* FEAT_LS64 feature does not feature any trap
bits, it's only the addition of the ACCDATA_EL1 system register that
adds these traps and the SCR_EL3 bits.
Change-Id: Ie3e2ca2d9c4fbbd45c0cc6089accbb825579138a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
