Provide a helper to detect the enabled UART device during runtime. This
lower the integration effort and make it more straight forward for
'simple' use-cases with a single UART enabled. If multiple UARTs are
enabled the first enabled is returned.
The auto-detection is enabled by setting IMX_BOOT_UART_BASE=0 to keep
the backward compatibility. For more advanced use-cases (multiple UARTs
are enabled) the user still has to provide the correct base address.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I300a167e1a10f9aa991c8d1c3efe2c6b23f56c47
Adjusted BL2 maximum size as per total SRAM size.
Change-Id: Ic3b398574a17e8a784e7c4dbe3fe69d1fb2b5e16
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The Qualcomm X5 Modem (MDM9607) SoC is very similar to the existing
MSM8916, except for:
- Single core ARM Cortex-A7
- No GPU
- MMU-500 r2p4 instead of r0p0 (need to clear CACHE_LOCK bit)
- Different default BL31/BL33 address and UART number
Make the existing MSM8916 platform port usable for MDM9607 as well by
adding some minimal if statements where necessary plus the platform
make files for mdm9607.
Change-Id: I4dd02c8e29af6282d8d828c3027c5e333459ba36
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Some Qualcomm modem platforms (MDM*) are quite similar to MSM8916
except that there is just a single CPU core. This requires some special
handling:
- There is no GPU so the GPU SMMU also does not exist.
- Looking closely at dumps of the MMIO register regions reveals that
some of the register addresses are slightly different.
Add the necessary checks for this to allow building for those
platforms.
No functional change for existing platforms.
Change-Id: I0380ac3734876243e970a55d8bec5a8247175343
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
The Qualcomm Snapdragon 615 (MSM8939) SoC is very similar to the
existing MSM8916, except for:
- Two clusters with ARM Cortex-A53 cores
- CCI-400
Make the existing MSM8916 platform port usable for MSM8939 as well by
adding some minimal if statements where necessary plus the platform
make files for msm8939.
Change-Id: I8cda83dc642f62222f984a42eec14de5df4c11e3
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
On platforms with multiple CPU clusters the L2 cache will be only on
for the cluster of the boot CPU. Add the necessary sequence to power it
up for secondary clusters similar to the CPU boot sequence.
No functional change for platforms with a single cluster. The new code
is discarded entirely in this case.
Change-Id: I3d3bce519a8a10ef5278d74d81acf59123e00454
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
The MSM8939 SoC is very similar to MSM8916 but uses an ARM CCI-400
for cache coherence between the two CPU clusters. Add the necessary
code to initialize it with the existing driver.
No functional change for platforms with a single cluster. The CCI
related code is discarded entirely in this case.
Change-Id: I041d60222d8d2aeca53b392934c87280c66b0db0
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Some Qualcomm platforms similar to MSM8916 have multiple CPU clusters.
In this case, some of the hardware blocks are duplicated and must be
configured separately.
Refactor the code to handle additional clusters by introducing loops
and some conditionals.
No functional change for existing single cluster platforms.
Change-Id: I5b4b1ad2a1adde559d5b79b7698afe73733b2e90
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
The Qualcomm Snapdragon 210 (MSM8909) SoC is very similar to the
existing MSM8916, except for:
- ARM Cortex-A7 instead of Cortex-A53 (AArch32-only)
- MMU-500 r2p0 instead of r0p0 (need to clear CACHE_LOCK bit)
- Different default BL31 address and UART number
Make the existing MSM8916 platform port usable for MSM8909 as well by
adding some minimal if statements where necessary plus the platform
make files for msm8909.
Change-Id: I8eca5bd8f2486cc2174562fb5de28f8dffa0d874
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Newer Qualcomm platforms similar to MSM8916 use MMU-500 r2p0+ instead
of MMU-500 r0p0. On these versions it is necessary to clear the
SMMU_sACR.CACHE_LOCK bit to allow the normal world to write to
SMMU_CBn_ACTLR. Without this Linux shows a warning and is unable to
workaround the errata in MMU-500:
arm-smmu 1e00000.iommu: Failed to disable prefetcher
[errata #841119 and #826419], check ACR.CACHE_LOCK
Handle this dynamically at runtime by enabling all the necessary SMMU
clocks and check the IDR7 register for MMU-500 r2p0+. This must be
applied to both SMMUs on the platform: APPS and GPU.
While at it clean up the clock handling: Leave the SMMU clocks on
because the normal world will need it again while booting. But make
sure the vote register of the RPM co-processor does not keep these
clocks always-on. For some reasons some platforms seem to have a
non-zero reset value for GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE.
Change-Id: I34cf7d3f2db977b0930eb6e64a870ecaf02a7573
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
According to the coding style all conditional statements (such as if,
for, while, do) must use braces regardless of the number of the
statements in the body [1].
Fix this for the code inside plat/qti/msm8916.
[1]: https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#conditional-statement-bodies
Change-Id: I74f2e65aa2b3a65899e37dfd3f481d90fb15531c
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
* changes:
refactor(tc): print RSS interface test PSA status
test(tc): test for AP/RSS interface for ROTPK
feat(psa): interface with RSS for retrieving ROTPK
Moving all PLATFORM_TESTS into platform test makefile
Change-Id: I31821e9e69d916d12ae4c804df26f07fb523c835
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrupt.
Moreover, once the platform has handled the interrupt successfully,
SPMD must deactivate the interrupt.
The rationale behind this decision is SPMD framework is well suited to
perform interrupt management at GIC boundary while the platform handler
is well equipped to deal with the device interface related to the
interrupt.
This patch also fixes a bug in the error code returned upon invocation
of FFA_EL3_INTR_HANDLE from normal world.
Change-Id: If8fef51899e25f966038cc01ec58c84ee25e88eb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Adding PSA status to print statement upon failing communication
initialization, non-volatile counter, and rotpk read interface calls in
platform_tests.
Change-Id: Ia949cc2d18e93efb68f663d0c4e5500ca9021a94
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Adding new test for AP/RSS interface for reading ROTPK for
each 3 types of ROTPKs for: CCA, secure, and non-secure firmware.
Enabled by PLATFORM_TEST=rss-rotpk.
Update to print output when AP/RSS interface platform tests
pass to be able to reuse expect script functionality in CI.
Change-Id: Icc50b090e18a272378751fda104d209738b5b70c
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
We limited the r/w permission of some register groups for security
concerns. These regitser groups should not be accessed by domain 3 or
domain 5.
Change-Id: I2188da88d9e10a931d87bda14dc7dca46633dcd8
Signed-off-by: Chungying Lu <chungying.lu@mediatek.corp-partner.google.com>
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR_LVL`, which otherwise would result in undefined behavior.
This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.
Change-Id: Ib9ff606b7eebd8a8224891a0d239a4e13311fe2a
Signed-off-by: Wing Li <wingers@google.com>
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR_LVL`, which otherwise would result in undefined behavior.
This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.
Change-Id: Ia0fb1e68af9320370325642b17c4569e9580aa3a
Signed-off-by: Wing Li <wingers@google.com>
Currently we have a large series of errata_refactor patches pending
and they are all failing on arm_fpga build when we add errata_framework.
Errata framework can cause the size to grow and thus causing build
failure on bl31 size. This as of today is blocking us from
merging most of our changes as it will introduce a CI failure.
As an workaround we try to just reduce the arm_fpga build by a710
platform, we have a715 and a720 which should be ok I think.
Once everyone are available for further discussion we could revert this
change back and discuss further whats the right approach.
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I96a821e10aaecf04db7407fb2df38012839bfb94
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
* changes:
docs(imx9): add imx93 platform
feat(imx93): add OPTEE support
feat(imx93): protect OPTEE memory to secure access only
feat(imx93): add cpuidle and basic suspend support
feat(imx93): add reset & poweroff support
feat(imx93): allow SoC masters access to system TCM
feat(imx93): update the ocram trdc config for did10
feat(imx93): add the basic support
feat(imx93): add the trdc driver
build(changelog): add new scopes for nxp imx platform
Update 'PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE' to
'PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE' which is defined
in the PSA Certified Attestation API spec.
Change-Id: I5837fea552e6fe18a203412eb90d41e2f90ad6f1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
The fact that this was void instead of int, as required, caused
the test-running code to assume that the tests always failed.
Fixing the return type fixes the always-tests-failing bug.
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: Ief55fe15c437c87dac1d03419a8e148f5d864b8d
Add support to qemu "neoverse-v1" cpu for "qemu" ('virt') platform.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I4821115b54ca596fe27cb9d74a95429cd3cb21d9
This patch is used to enable platform enablement for
Agilex5 SoC FPGA.
New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU
3. Added ATF->Linux boot option
4. Added SMP support
5. Added HPS bridges support
6. Added EMULATOR support
7. Added DDR support
8. Added GICv3 Redistirbution init
9. Added SDMMC/NAND/Combo Phy support
10. Updated GIC as secure access
11. Added CCU driver support
12. Updated product name -> Agilex5
13. Updated register address based on y22ww52.2 RTL
14. Updated system counter freq to 400MHz
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009
This patch is used to implement CCU driver for
Agilex5 SoC FPGA.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic5e38499c969486682761c00d9e050e60c883725
This patch is used to implement VAB to support for
Agilex5 SoC FPGA.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I421f11225cd549f35f06e87b8ad2c44b716b2a78
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
This patch is used to implement ddr driver to
support IO96b for Agilex5 SoC FPGA.
1. Added DDR support.
2. Updated product name -> Agilex5
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ibda053de6dbec4a0f12f011d8feeb6c5890fc7a4
This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
1. Added power manager support.
2. Updated product name -> Agilex5
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: If0630c5088a1bc63dff64b1aab225fc70effa6e3
This patch is used to implement
1. Cold/Warm reset and SMP support for
Agilex5 SoC FPGA
2. Updated product name -> Agilex5
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2c0645bcbf3a5907a4c79f35cffe674920b48f9d
