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feat(versal-net): ddr address reservation in dtb at runtime

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When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
This commit is contained in:
Amit Nagal 2023-07-10 10:43:29 +05:30 • committed by Akshay Belsare
parent 56d1857efc
commit 46a08aab4c
3 changed files with 29 additions and 8 deletions

10
plat/xilinx/versal_net/bl31_versal_net_setup.c
View file

@ -12,17 +12,15 @@
#include <bl31/bl31.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/fdt_fixup.h>
#include <common/fdt_wrappers.h>
#include <drivers/arm/dcc.h>
#include <drivers/arm/pl011.h>
#include <drivers/console.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <libfdt.h>
#include <plat/common/platform.h>
#include <plat_arm.h>
#include <plat_fdt.h>
#include <plat_private.h>
#include <plat_startup.h>
#include <pm_api_sys.h>
@ -226,6 +224,8 @@ static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
void bl31_platform_setup(void)
{
prepare_dtb();
/* Initialize the gic cpu and distributor interfaces */
plat_versal_net_gic_driver_init();
plat_versal_net_gic_init();
@ -250,6 +250,10 @@ void bl31_plat_runtime_setup(void)
void bl31_plat_arch_setup(void)
{
const mmap_region_t bl_regions[] = {
#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
MT_MEMORY | MT_RW | MT_NS),
#endif
MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,

20
plat/xilinx/versal_net/include/platform_def.h
View file

@ -84,13 +84,25 @@
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U)
#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
#define MAX_MMAP_REGIONS U(10)
#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
#define PLAT_OCM_BASE U(0xBBF00000)
#define PLAT_OCM_LIMIT U(0xBC000000)
#define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT))
#ifndef MAX_MMAP_REGIONS
#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
#define MAX_MMAP_REGIONS 9
#else
#define MAX_MMAP_REGIONS U(9)
#define MAX_MMAP_REGIONS 8
#endif
#endif
#define MAX_XLAT_TABLES U(8)
#ifndef MAX_XLAT_TABLES
#define MAX_XLAT_TABLES U(9)
#endif
#define CACHE_WRITEBACK_SHIFT U(6)
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)

7
plat/xilinx/versal_net/platform.mk
View file

@ -65,6 +65,10 @@ endif
$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE}))
ifdef XILINX_OF_BOARD_DTB_ADDR
$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
endif
PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
-Iplat/xilinx/common/include/ \
-Iplat/xilinx/common/ipi_mailbox_service/ \
@ -101,7 +105,8 @@ BL31_SOURCES += plat/xilinx/common/pm_service/pm_api_sys.c \
else
BL31_SOURCES += ${PLAT_PATH}/plat_psci.c
endif
BL31_SOURCES += plat/xilinx/common/plat_startup.c \
BL31_SOURCES += plat/xilinx/common/plat_fdt.c \
plat/xilinx/common/plat_startup.c \
plat/xilinx/common/ipi.c \
plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
plat/xilinx/common/versal.c \