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https://github.com/ARM-software/arm-trusted-firmware.git
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feat(intel): ddr driver for Agilex5 SoC FPGA
This patch is used to implement ddr driver to support IO96b for Agilex5 SoC FPGA. 1. Added DDR support. 2. Updated product name -> Agilex5 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: Ibda053de6dbec4a0f12f011d8feeb6c5890fc7a4
This commit is contained in:
Jit Loon Lim
parent
a8bf898f02
commit
29461e4c88
2 changed files with 454 additions and 0 deletions
342
plat/intel/soc/common/drivers/ddr/ddr.c
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342
plat/intel/soc/common/drivers/ddr/ddr.c
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@ -0,0 +1,342 @@
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/*
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* Copyright (c) 2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <common/debug.h>
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#include "ddr.h"
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#include <lib/mmio.h>
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#include "socfpga_handoff.h"
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int ddr_calibration_check(void)
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{
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// DDR calibration check
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int status = 0;
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uint32_t u32data_read = 0;
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NOTICE("DDR: Access address 0x%x:...\n", IO96B_0_REG_BASE);
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u32data_read = mmio_read_32(IO96B_0_REG_BASE);
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NOTICE("DDR: Access address 0x%x: read 0x%04x\n", IO96B_0_REG_BASE, u32data_read);
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if (u32data_read == -EPERM) {
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status = -EPERM;
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assert(u32data_read);
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}
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u32data_read = 0x0;
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NOTICE("DDR: Access address 0x%x: ...\n", IO96B_1_REG_BASE);
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u32data_read = mmio_read_32(IO96B_1_REG_BASE);
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NOTICE("DDR: Access address 0x%x: read 0x%04x\n", IO96B_1_REG_BASE, u32data_read);
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if (u32data_read == -EPERM) {
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status = -EPERM;
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assert(u32data_read);
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}
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return status;
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}
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int iossm_mb_init(void)
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{
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// int status;
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// Update according to IOSSM mailbox spec
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// if (status) {
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// return status;
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// }
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return 0;
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}
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int wait_respond(uint16_t timeout)
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{
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uint32_t status = 0;
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uint32_t count = 0;
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uint32_t data = 0;
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/* Wait status command response ready */
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do {
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data = mmio_read_32(IO96B_CSR_REG(CMD_RESPONSE_STATUS));
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count++;
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if (count >= timeout) {
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return -ETIMEDOUT;
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}
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} while (STATUS_COMMAND_RESPONSE(data) != STATUS_COMMAND_RESPONSE_READY);
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status = (data & STATUS_GENERAL_ERROR_MASK) >> STATUS_GENERAL_ERROR_OFFSET;
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if (status != 0) {
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return status;
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}
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status = (data & STATUS_CMD_RESPONSE_ERROR_MASK) >> STATUS_CMD_RESPONSE_ERROR_OFFSET;
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if (status != 0) {
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return status;
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}
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return status;
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}
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int iossm_mb_read_response(void)
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{
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uint32_t status = 0;
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unsigned int i;
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uint32_t resp_data[IOSSM_RESP_MAX_WORD_SIZE];
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uint32_t resp_param_reg;
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// Check STATUS_CMD_RESPONSE_DATA_PTR_VALID in
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// STATUS_COMMAND_RESPONSE to ensure data pointer response
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/* Read CMD_RESPONSE_STATUS and CMD_RESPONSE_DATA_* */
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resp_data[0] = mmio_read_32(IO96B_CSR_REG(CMD_RESPONSE_STATUS));
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resp_data[0] = (resp_data[0] & CMD_RESPONSE_DATA_SHORT_MASK) >>
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CMD_RESPONSE_DATA_SHORT_OFFSET;
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resp_param_reg = CMD_RESPONSE_STATUS;
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for (i = 1; i < IOSSM_RESP_MAX_WORD_SIZE; i++) {
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resp_param_reg = resp_param_reg - CMD_RESPONSE_OFFSET;
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resp_data[i] = mmio_read_32(IO96B_CSR_REG(resp_param_reg));
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}
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/* Wait for STATUS_COMMAND_RESPONSE_READY*/
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status = wait_respond(1000);
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/* Read CMD_RESPONSE_STATUS and CMD_RESPONSE_DATA_* */
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mmio_setbits_32(STATUS_COMMAND_RESPONSE(IO96B_CSR_REG(
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CMD_RESPONSE_STATUS)),
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STATUS_COMMAND_RESPONSE_READY_CLEAR);
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return status;
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}
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int iossm_mb_send(uint32_t cmd_target_ip_type, uint32_t cmd_target_ip_instance_id,
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uint32_t cmd_type, uint32_t cmd_opcode, uint32_t *args,
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unsigned int len)
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{
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unsigned int i;
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uint32_t status = 0;
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uint32_t cmd_req;
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uint32_t cmd_param_reg;
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cmd_target_ip_type = (cmd_target_ip_type & CMD_TARGET_IP_TYPE_MASK) <<
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CMD_TARGET_IP_TYPE_OFFSET;
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cmd_target_ip_instance_id = (cmd_target_ip_instance_id &
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CMD_TARGET_IP_INSTANCE_ID_MASK) <<
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CMD_TARGET_IP_INSTANCE_ID_OFFSET;
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cmd_type = (cmd_type & CMD_TYPE_MASK) << CMD_TYPE_OFFSET;
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cmd_opcode = (cmd_opcode & CMD_OPCODE_MASK) << CMD_OPCODE_OFFSET;
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cmd_req = cmd_target_ip_type | cmd_target_ip_instance_id | cmd_type |
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cmd_opcode;
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/* send mailbox request */
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IOSSM_MB_WRITE(IO96B_CSR_REG(CMD_REQ), cmd_req);
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if (len != 0) {
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cmd_param_reg = CMD_REQ;
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for (i = 0; i < len; i++) {
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cmd_param_reg = cmd_param_reg - CMD_PARAM_OFFSET;
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IOSSM_MB_WRITE(IO96B_CSR_REG(cmd_param_reg), args[i]);
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}
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}
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status = iossm_mb_read_response();
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if (status != 0) {
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return status;
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}
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return status;
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}
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int ddr_iossm_mailbox_cmd(uint32_t cmd_opcode)
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{
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// IOSSM
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uint32_t status = 0;
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unsigned int i = 0;
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uint32_t payload[IOSSM_CMD_MAX_WORD_SIZE] = {0U};
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switch (cmd_opcode) {
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case CMD_INIT:
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status = iossm_mb_init();
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break;
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case OPCODE_GET_MEM_INTF_INFO:
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status = iossm_mb_send(0, 0, MBOX_CMD_GET_SYS_INFO,
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OPCODE_GET_MEM_INTF_INFO, payload, i);
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break;
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case OPCODE_GET_MEM_TECHNOLOGY:
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status = iossm_mb_send(0, 0, MBOX_CMD_GET_MEM_INFO,
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OPCODE_GET_MEM_TECHNOLOGY, payload, i);
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break;
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case OPCODE_GET_MEM_WIDTH_INFO:
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status = iossm_mb_send(0, 0, MBOX_CMD_GET_MEM_INFO,
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OPCODE_GET_MEM_WIDTH_INFO, payload, i);
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break;
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case OPCODE_ECC_ENABLE_STATUS:
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status = iossm_mb_send(0, 0,
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MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_ECC_ENABLE_STATUS,
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payload, i);
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break;
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case OPCODE_ECC_INTERRUPT_MASK:
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// payload[i] = CMD_PARAM_0 [16:0]: ECC_INTERRUPT_MASK
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status = iossm_mb_send(0, 0,
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MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_ECC_INTERRUPT_MASK,
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payload, i);
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break;
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case OPCODE_ECC_SCRUB_MODE_0_START:
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// payload[i] = CMD_PARAM_0 [15:0]: ECC_SCRUB_INTERVAL
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//i++;
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// payload[i] = CMD_PARAM_1 [11:0]: ECC_SCRUB_LEN
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//i++;
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// payload[i] = CMD_PARAM_2 [0:0]: ECC_SCRUB_FULL_MEM
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//i++;
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// payload[i]= CMD_PARAM_3 [31:0]: ECC_SCRUB_START_ADDR [31:0]
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//i++;
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// payload[i] = CMD_PARAM_4 [5:0]: ECC_SCRUB_START_ADDR [36:32]
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//i++;
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// payload[i] = CMD_PARAM_5 [31:0]: ECC_SCRUB_END_ADDR [31:0]
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//i++;
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// payload[i] = CMD_PARAM_6 [5:0]: ECC_SCRUB_END_ADDR [36:32]
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//i++;
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status = iossm_mb_send(0, 0,
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MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_ECC_SCRUB_MODE_0_START,
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payload, i);
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break;
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case OPCODE_ECC_SCRUB_MODE_1_START:
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// payload[i] = CMD_PARAM_0 [15:0]: ECC_SCRUB_IDLE_CNT
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//i++;
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// payload[i] = CMD_PARAM_1 [11:0]: ECC_SCRUB_LEN
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//i++;
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// payload[i] = CMD_PARAM_2 [0:0]: ECC_SCRUB_FULL_MEM
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//i++;
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// payload[i] = CMD_PARAM_3 [31:0]: ECC_SCRUB_START_ADDR [31:0]
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//i++;
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// payload[i] = CMD_PARAM_4 [5:0]: ECC_SCRUB_START_ADDR [36:32]
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//i++;
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// payload[i] = CMD_PARAM_5 [31:0]: ECC_SCRUB_END_ADDR [31:0]
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//i++;
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// payload[i] = CMD_PARAM_6 [5:0]: ECC_SCRUB_END_ADDR [36:32]
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//i++;
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status = iossm_mb_send(0, 0,
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MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_ECC_SCRUB_MODE_1_START,
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payload, i);
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break;
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case OPCODE_BIST_RESULTS_STATUS:
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status = iossm_mb_send(0, 0,
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MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_BIST_RESULTS_STATUS,
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payload, i);
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break;
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case OPCODE_BIST_MEM_INIT_START:
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status = iossm_mb_send(0, 0,
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MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_BIST_MEM_INIT_START,
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payload, i);
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break;
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case OPCODE_TRIG_MEM_CAL:
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status = iossm_mb_send(0, 0, MBOX_CMD_TRIG_MEM_CAL_OP,
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OPCODE_TRIG_MEM_CAL, payload, i);
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break;
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default:
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break;
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}
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if (status == -EPERM) {
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assert(status);
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}
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return status;
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}
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int ddr_config_handoff(handoff *hoff_ptr)
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{
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/* Populate DDR handoff data */
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/* TODO: To add in DDR handoff configuration once available */
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return 0;
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}
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// DDR firewall and non secure access
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void ddr_enable_ns_access(void)
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{
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/* Please set the ddr non secure registers accordingly */
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mmio_setbits_32(CCU_REG(DMI0_DMIUSMCTCR),
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CCU_DMI_ALLOCEN | CCU_DMI_LOOKUPEN);
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mmio_setbits_32(CCU_REG(DMI1_DMIUSMCTCR),
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CCU_DMI_ALLOCEN | CCU_DMI_LOOKUPEN);
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/* TODO: To add in CCU NCORE OCRAM bypass mask for non secure registers */
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NOTICE("DDR non secure configured\n");
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}
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void ddr_enable_firewall(void)
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{
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/* Please set the ddr firewall registers accordingly */
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/* TODO: To add in CCU NCORE OCRAM bypass mask for firewall registers */
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NOTICE("DDR firewall enabled\n");
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}
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bool is_ddr_init_in_progress(void)
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{
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uint32_t reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0));
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if (reg & SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0_MASK) {
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return true;
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}
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return false;
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}
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int ddr_init(void)
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{
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// DDR driver initialization
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int status = -EPERM;
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uint32_t cmd_opcode = 0;
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// Check and set Boot Scratch Register
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if (is_ddr_init_in_progress()) {
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return status;
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}
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mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0), 0x01);
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// Populate DDR handoff data
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handoff reverse_handoff_ptr;
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if (!socfpga_get_handoff(&reverse_handoff_ptr)) {
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assert(status);
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}
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status = ddr_config_handoff(&reverse_handoff_ptr);
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if (status == -EPERM) {
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assert(status);
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}
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// CCU and firewall setup
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ddr_enable_ns_access();
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ddr_enable_firewall();
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// DDR calibration check
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status = ddr_calibration_check();
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if (status == -EPERM) {
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assert(status);
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}
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// DDR mailbox command
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status = ddr_iossm_mailbox_cmd(cmd_opcode);
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if (status != 0) {
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assert(status);
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}
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// Check and set Boot Scratch Register
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mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0), 0x00);
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NOTICE("DDR init successfully\n");
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return status;
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}
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112
plat/intel/soc/common/drivers/ddr/ddr.h
Normal file
112
plat/intel/soc/common/drivers/ddr/ddr.h
Normal file
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@ -0,0 +1,112 @@
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/*
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* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DDR_H
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#define DDR_H
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#include <lib/mmio.h>
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#include "socfpga_handoff.h"
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/* MACRO DEFINATION */
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#define IO96B_0_REG_BASE 0x18400000
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#define IO96B_1_REG_BASE 0x18800000
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#define IO96B_CSR_BASE 0x05000000
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#define IO96B_CSR_REG(reg) (IO96B_CSR_BASE + reg)
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#define IOSSM_CMD_MAX_WORD_SIZE 7U
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#define IOSSM_RESP_MAX_WORD_SIZE 4U
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#define CCU_REG_BASE 0x1C000000
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#define DMI0_DMIUSMCTCR 0x7300
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#define DMI1_DMIUSMCTCR 0x8300
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#define CCU_DMI_ALLOCEN BIT(1)
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#define CCU_DMI_LOOKUPEN BIT(2)
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#define CCU_REG(reg) (CCU_REG_BASE + reg)
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// CMD_RESPONSE_STATUS Register
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#define CMD_RESPONSE_STATUS 0x45C
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#define CMD_RESPONSE_OFFSET 0x4
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#define CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16)
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#define CMD_RESPONSE_DATA_SHORT_OFFSET 16
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#define STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5)
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#define STATUS_CMD_RESPONSE_ERROR_OFFSET 5
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#define STATUS_GENERAL_ERROR_MASK GENMASK(4, 1)
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#define STATUS_GENERAL_ERROR_OFFSET 1
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#define STATUS_COMMAND_RESPONSE_READY 0x1
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#define STATUS_COMMAND_RESPONSE_READY_CLEAR 0x0
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#define STATUS_COMMAND_RESPONSE_READY_MASK 0x1
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#define STATUS_COMMAND_RESPONSE_READY_OFFSET 0
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#define STATUS_COMMAND_RESPONSE(x) (((x) & \
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STATUS_COMMAND_RESPONSE_READY_MASK) >> \
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STATUS_COMMAND_RESPONSE_READY_OFFSET)
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// CMD_REQ Register
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#define CMD_STATUS 0x400
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#define CMD_PARAM 0x438
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#define CMD_REQ 0x43C
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#define CMD_PARAM_OFFSET 0x4
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#define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29)
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#define CMD_TARGET_IP_TYPE_OFFSET 29
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#define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24)
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#define CMD_TARGET_IP_INSTANCE_ID_OFFSET 24
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#define CMD_TYPE_MASK GENMASK(23, 16)
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#define CMD_TYPE_OFFSET 16
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#define CMD_OPCODE_MASK GENMASK(15, 0)
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#define CMD_OPCODE_OFFSET 0
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#define CMD_INIT 0
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#define OPCODE_GET_MEM_INTF_INFO 0x0001
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#define OPCODE_GET_MEM_TECHNOLOGY 0x0002
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#define OPCODE_GET_MEM_WIDTH_INFO 0x0004
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#define OPCODE_TRIG_MEM_CAL 0x000A
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#define OPCODE_ECC_ENABLE_STATUS 0x0102
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#define OPCODE_ECC_INTERRUPT_MASK 0x0105
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#define OPCODE_ECC_SCRUB_MODE_0_START 0x0202
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#define OPCODE_ECC_SCRUB_MODE_1_START 0x0203
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#define OPCODE_BIST_RESULTS_STATUS 0x0302
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#define OPCODE_BIST_MEM_INIT_START 0x0303
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// Please update according to IOSSM mailbox spec
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#define MBOX_ID_IOSSM 0x00
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#define MBOX_CMD_GET_SYS_INFO 0x01
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// Please update according to IOSSM mailbox spec
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#define MBOX_CMD_GET_MEM_INFO 0x02
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#define MBOX_CMD_TRIG_CONTROLLER_OP 0x04
|
||||
#define MBOX_CMD_TRIG_MEM_CAL_OP 0x05
|
||||
#define MBOX_CMD_POKE_REG 0xFD
|
||||
#define MBOX_CMD_PEEK_REG 0xFE
|
||||
#define MBOX_CMD_GET_DEBUG_LOG 0xFF
|
||||
// Please update according to IOSSM mailbox spec
|
||||
#define MBOX_CMD_DIRECT 0x00
|
||||
|
||||
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0_MASK 0x01
|
||||
|
||||
#define IOSSM_MB_WRITE(addr, data) mmio_write_32(addr, data)
|
||||
|
||||
/* FUNCTION DEFINATION */
|
||||
int ddr_calibration_check(void);
|
||||
|
||||
int iossm_mb_init(void);
|
||||
|
||||
int iossm_mb_read_response(void);
|
||||
|
||||
int iossm_mb_send(uint32_t cmd_target_ip_type, uint32_t cmd_target_ip_instance_id,
|
||||
uint32_t cmd_type, uint32_t cmd_opcode, uint32_t *args,
|
||||
unsigned int len);
|
||||
|
||||
int ddr_iossm_mailbox_cmd(uint32_t cmd);
|
||||
|
||||
int ddr_init(void);
|
||||
|
||||
int ddr_config_handoff(handoff *hoff_ptr);
|
||||
|
||||
void ddr_enable_ns_access(void);
|
||||
|
||||
void ddr_enable_firewall(void);
|
||||
|
||||
bool is_ddr_init_in_progress(void);
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue