Transfer List Compiler is a command line tool that enables the static
generation of TL's compliant with version 0.9 of the firmware handoff
specification. The intent of this tool is to support information passing
via the firmware handoff framework to bootloaders that run without
preceding images (i.e. `RESET_TO_BL31`).
It currently allows for TL's to be statically generated from blobs of
data, and modified by removing/adding TE's. Future work will provide
support for TL generation from configuration file.
Change-Id: Iff670842e34c9ad18eac935248ee2aece43dc533
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Co-authored-by: Charlie Bareham <charlie.bareham@arm.com>
* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: add support for AXP313 PMIC
feat(allwinner): h616: add I2C PMIC support
refactor(allwinner): h616: prepare for more than one PMIC model
To support UEFI secure variable service,
StandaloneMm which runs in BL32 should know flash areas.
Add flash memory areas and system register region
so that StandaloneMm access to flash storages.
Change-Id: I803bda9664a17a0b978ebff90974eaf5442a91cd
Signed-off-by: levi.yun <yeoreum.yun@arm.com>
OP-TEE enables the use case of a secure interrupt triggered by the UART
driver. This interrupt is routed by FFA_INTERRUPT interface to OP-TEE.
Define the UART interrupt in the FF-A device region node.
Without this change, OPTEE panics at the boot with the following:
| I/TC: No non-secure external DT
| I/TC: manifest DT found
| I/TC: OP-TEE version: 4.3.0-23-gfcd8750677db
| I/TC: WARNING: This OP-TEE configuration might be insecure!
| I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
| I/TC: Primary CPU initializing
| E/TC:0 0 assertion '!res' failed at core/drivers/hfic.c:56 <hfic_op_enable>
| E/TC:0 0 Panic at core/kernel/assert.c:28 <_assert_break>
| E/TC:0 0 TEE load address @ 0x6284000
Change-Id: Icddcdfd032315aeee65ba3100f3a6b470a74435d
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* changes:
fix(rmmd): remove the assert check for RMM_BASE
fix(std_svc): continue boot if rmmd_setup fails
fix(rmmd): ignore SMC FID when RMM image is not present
fix(rmmd): fail gracefully if RME is not enabled
fix(rmmd): handle RMMD manifest loading failure
Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.
Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.
Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.
* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.
* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.
* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".
* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.
Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.
Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
* changes:
build(deps): bump braces
build(deps): bump the pip group across 1 directory with 2 updates
build(deps): bump the pip group across 1 directory with 7 updates
A macro 'sysreg_bitfield_insert_from_gpr' is introduced for inserting
bitfield from a general register.
Change-Id: I7288a13d70d98e23dc7a93287b04b493ffce9171
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Add DT binding for Arm DSU PMU node.
Change-Id: Iadfb5d3bb3f69c7a771516180d1c165e60eef51d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set for all cores, so set these bits in platform reset handler.
Change-Id: I1db6915939727f0909c05c8b103e37984aadb443
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
The comment for plat_reset_handler doesn't make sense. It is likely a
copy-and-paste error while adding the code, so remove it.
Change-Id: Iab8c8c799c184fa99966770d47ecb11bbc640515
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
The system register actlr_el2 can be set during CPU or platform reset
handler. E.g. on Arm Total Compute platform, the CLUSTERPMUEN bit of
actlr_el2 is set in the platform reset handler to enable the write
access to DSU PMU registers from EL1. However, as EL2 context gets
restored without saving it beforehand during jump to SPM and next NS
image, therefore, the initialized value of actlr_el2 is not retained.
To fix this issue, keep track of actlr_el2 value during the EL2 context
initialization. This applies for both secure and non-secure security
state.
Change-Id: I1bd7b984216c042c056ad20c6724bedce5a6a3e2
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Include platform.h file in order to remove following compiler errors,
as some warnings are being treated as errors now.
error: implicit declaration of function
'plat_core_pos_by_mpidr'[-Wimplicit-function-declaration]
Change-Id: Ie223e11e138ec9b0eef7342f450b90b215a49b15
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was changed from 0x40_b10b
(3 bytes) to 4a0f_b10b (4 bytes).
As updating of TL's signature, register value of x1/r1 should be:
In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b -> masked range value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).
Therefore, it requires to separate mask and shift value for register
convention version field when sets each r1/x1.
This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.
2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.
This change is breaking change. It requires some patch for other
softwares (u-boot[4], optee[5]).
Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: 5aa7aa1d3a [3]
Link: https://lists.denx.de/pipermail/u-boot/2024-July/558628.html [4]
Link: https://github.com/OP-TEE/optee_os/pull/6933 [5]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ie417e054a7a4c192024a2679419e99efeded1705
In a system enabled with RME, the function
'xlat_get_mem_attributes_internal' fails to accurately provide
'output PA space' for Realm and Root memory because it does not
consider the 'nse' bit in page table descriptor.
This patch resolves the issue by extracting the 'nse' bit value.
As a result, it ensures correct retrieval of attributes
in RME-enabled systems while maintaining unaffected attribute
retrieval for non-RME systems.
Change-Id: If2d01545b921c9074f48c52a98027ff331e14237
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
This commit streamlines directory creation by introducing a single
pattern rule to automatically make directories for which there is a
dependency.
We currently use several macros to generate rules to create directories
upon dependence, which is a significant amount of code and a lot of
redundancy. The rule introduced by this change represents a catch-all:
any rule dependency on a path ending in a forward slash is automatically
created.
Now, rules can rely on an unordered dependency (`|`) on `$$(@D)/` which,
when secondary expansion is enabled, expands to the directory of the
target being built, e.g.:
build/main.o: main.c | $$(@D)/ # automatically creates `build/`
Change-Id: I7e554efa2ac850e779bb302fd9c7fbb239886c9f
Signed-off-by: Chris Kay <chris.kay@arm.com>
This patch removes the assert from rmmd_setup() that checks if the
RMM image PC is equal to RMM_BASE. The RMM image can be relocated to
any address in the DRAM by the previous bootloader. So, providing the
RMM base address at compile time is not feasible for such platforms.
The assert check is now replaced with a runtime check for the RMM image.
Change-Id: I568cdb6f76f41d0dcdc7a95feb75e252a7c5c930
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch allows the boot sequence to continue even if
rmmd_setup() fails. This allows platforms to use the same
RME-enabled image to support the scenarios where RMM image
is not present.
Change-Id: Ie4de15fb98ae7226eda410e15f1a650108dd8fb3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch marks the RMM boot as failed, to ignore the SMC
FID for the RMM at runtime, if RMM image is not present on
the platform.
Change-Id: I3c19d886d32c56837a1a0d260d5204da8b2d12f1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch converts the assert check for RME presence into
a runtime check and returns an error to fail gracefully. This
allows platforms to use the same image on boards that do not
support RME too.
Change-Id: I0cacdd7afd85ed3581e90ea81f0a51d076adb875
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch sets the rmm_boot_failed flag to true if the RMMD
manifest loading fails. This instructs the RMMD to ignore all
SMC FID for the RMM at runtime.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If61be6200e28fcea7a5ad697393e83679f488abc
* changes:
feat(fvp): add SPM manifest for OP-TEE at S-EL1 without S-EL2/Hafnium
fix(fvp): update the memory size allocated to optee at EL1
fix(fvp): add DRAM memory regions that linux kernel can share
feat(fvp): update FF-A version to v1.1 supported by optee
feat(fvp): replace managed-exit with ns-interrupts-action
fix(fvp): add optee specific mem-size attribute
fix(fvp): fix the FF-A optee manifest by adding the boot info node
modify the print logs when an erratum workaround does not
need to be applied to a certain revision/variant of the CPU.
Change-Id: I8f60636320f617ecd4ed88ee1fbf7a3e3e4517ee
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
When SPD is set to none, it means we don't run any secure OS on the
system. We should make this memory region available to kernel.
Change-Id: Ia83ff4a7d25de38a5d845b7ee1367bafed43bbdd
Signed-off-by: Yidi Lin <yidilin@chromium.org>
This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6d2b614affb9067b2bc3d7bf0ae7d169d031592a
This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a
* changes:
feat(nxp-clk): set rate for clock fixed divider
feat(nxp-clk): add A53 clock objects
feat(nxp-clk): set rate for PLL divider objects
feat(nxp-clk): set rate for PLL objects
