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https://github.com/ARM-software/arm-trusted-firmware.git
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Merge changes from topic "h616_pmics" into integration
* changes: feat(allwinner): adjust H616 L2 cache size in DTB feat(allwinner): h616: add support for AXP717 PMIC feat(allwinner): h616: add support for AXP313 PMIC feat(allwinner): h616: add I2C PMIC support refactor(allwinner): h616: prepare for more than one PMIC model
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
55b4c5ceb2
5 changed files with 273 additions and 31 deletions
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@ -58,4 +58,12 @@ static inline void sunxi_prepare_dtb(void *fdt)
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}
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#endif
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#ifdef PLAT_sun50i_h616
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void sunxi_soc_fdt_fixup(void *dtb);
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#else
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static inline void sunxi_soc_fdt_fixup(void *dtb)
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{
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}
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#endif
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#endif /* SUNXI_PRIVATE_H */
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@ -34,6 +34,8 @@ void sunxi_prepare_dtb(void *fdt)
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}
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#endif
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sunxi_soc_fdt_fixup(fdt);
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if (sunxi_psci_is_scpi()) {
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ret = fdt_add_cpu_idle_states(fdt, sunxi_idle_states);
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if (ret < 0) {
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@ -18,5 +18,8 @@ ifeq (${SUNXI_PSCI_USE_SCPI}, 1)
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$(error "H616 does not support SCPI PSCI ops")
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endif
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BL31_SOURCES += drivers/allwinner/axp/axp805.c \
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BL31_SOURCES += common/fdt_wrappers.c \
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drivers/allwinner/axp/axp805.c \
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drivers/allwinner/sunxi_rsb.c \
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drivers/mentor/i2c/mi2cv.c \
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${AW_PLAT}/${PLAT}/sunxi_h616_dtb.c
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72
plat/allwinner/sun50i_h616/sunxi_h616_dtb.c
Normal file
72
plat/allwinner/sun50i_h616/sunxi_h616_dtb.c
Normal file
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@ -0,0 +1,72 @@
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/*
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* Copyright (c) 2024, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Amend the device tree to adjust the L2 cache size, which is different
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* between the revisions of the H616 chips: earlier versions have 256 KB of L2,
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* later versions 1 MB.
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* Read the cache ID registers and adjust the size and number of sets entries
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* in the L2 cache DT node.
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*/
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#include <common/fdt_wrappers.h>
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#include <lib/utils_def.h>
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#include <libfdt.h>
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#define CACHE_L1D 0x0
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#define CACHE_L1I 0x1
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#define CACHE_L2U 0x2
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#define CCSIDR_SETS_SHIFT 13
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#define CCSIDR_SETS_MASK GENMASK(14, 0)
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#define CCSIDR_ASSOC_SHIFT 3
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#define CCSIDR_ASSOC_MASK GENMASK(9, 0)
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#define CCSIDR_LSIZE_SHIFT 0
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#define CCSIDR_LSIZE_MASK GENMASK(2, 0)
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static uint32_t armv8_get_ccsidr(unsigned int sel)
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{
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uint32_t reg;
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__asm__ volatile ("msr CSSELR_EL1, %0\n" :: "r" (sel));
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__asm__ volatile ("mrs %0, CCSIDR_EL1\n" : "=r" (reg));
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return reg;
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}
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void sunxi_soc_fdt_fixup(void *dtb)
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{
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int node = fdt_path_offset(dtb, "/cpus/cpu@0");
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uint32_t phandle, ccsidr, cell;
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int sets, line_size, assoc;
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int ret;
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if (node < 0) {
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return;
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}
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ret = fdt_read_uint32(dtb, node, "next-level-cache", &phandle);
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if (ret != 0) {
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return;
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}
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node = fdt_node_offset_by_phandle(dtb, phandle);
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if (ret != 0) {
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return;
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}
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ccsidr = armv8_get_ccsidr(CACHE_L2U);
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sets = ((ccsidr >> CCSIDR_SETS_SHIFT) & CCSIDR_SETS_MASK) + 1;
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line_size = 16U << ((ccsidr >> CCSIDR_LSIZE_SHIFT) & CCSIDR_LSIZE_MASK);
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assoc = ((ccsidr >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1;
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cell = cpu_to_fdt32(sets);
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fdt_setprop(dtb, node, "cache-sets", &cell, sizeof(cell));
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cell = cpu_to_fdt32(line_size);
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fdt_setprop(dtb, node, "cache-line-size", &cell, sizeof(cell));
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cell = cpu_to_fdt32(sets * assoc * line_size);
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fdt_setprop(dtb, node, "cache-size", &cell, sizeof(cell));
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}
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@ -10,97 +10,254 @@
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/allwinner/axp.h>
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#include <drivers/allwinner/sunxi_rsb.h>
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#include <drivers/mentor/mi2cv.h>
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#include <lib/mmio.h>
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#include <libfdt.h>
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#include <sunxi_cpucfg.h>
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#include <sunxi_def.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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#define AXP305_I2C_ADDR 0x36
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#define AXP305_HW_ADDR 0x745
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#define AXP305_RT_ADDR 0x3a
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static uint16_t pmic_bus_addr;
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static uint8_t rsb_rt_addr;
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static bool is_using_rsb(void)
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{
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return rsb_rt_addr != 0;
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}
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static enum pmic_type {
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UNKNOWN,
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AXP305,
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AXP313,
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AXP717,
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} pmic;
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static uint8_t get_rsb_rt_address(uint16_t hw_addr)
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{
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switch (hw_addr) {
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case 0x3a3: return 0x2d;
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case 0x745: return 0x3a;
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}
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return 0;
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}
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int axp_read(uint8_t reg)
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{
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return rsb_read(AXP305_RT_ADDR, reg);
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uint8_t val;
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int ret;
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if (is_using_rsb()) {
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return rsb_read(rsb_rt_addr, reg);
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}
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ret = i2c_write(pmic_bus_addr, 0, 0, ®, 1);
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if (ret == 0) {
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ret = i2c_read(pmic_bus_addr, 0, 0, &val, 1);
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}
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if (ret) {
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ERROR("PMIC: Cannot read PMIC register %02x\n", reg);
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return ret;
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}
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return val;
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}
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int axp_write(uint8_t reg, uint8_t val)
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{
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return rsb_write(AXP305_RT_ADDR, reg, val);
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int ret;
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if (is_using_rsb()) {
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return rsb_write(rsb_rt_addr, reg, val);
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}
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ret = i2c_write(pmic_bus_addr, reg, 1, &val, 1);
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if (ret) {
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ERROR("PMIC: Cannot write PMIC register %02x\n", reg);
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}
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return ret;
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}
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static int rsb_init(void)
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static int rsb_init(int rsb_hw_addr)
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{
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int ret;
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ret = rsb_init_controller();
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if (ret)
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if (ret) {
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return ret;
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}
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/* Switch to the recommended 3 MHz bus clock. */
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ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
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if (ret)
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if (ret) {
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return ret;
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}
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/* Initiate an I2C transaction to switch the PMIC to RSB mode. */
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ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
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if (ret)
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if (ret) {
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return ret;
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}
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/* Associate the 8-bit runtime address with the 12-bit bus address. */
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ret = rsb_assign_runtime_address(AXP305_HW_ADDR, AXP305_RT_ADDR);
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if (ret)
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ret = rsb_assign_runtime_address(rsb_hw_addr, rsb_rt_addr);
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if (ret) {
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return ret;
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}
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return axp_check_id();
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return 0;
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}
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static int pmic_bus_init(uint16_t socid, uint16_t rsb_hw_addr)
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{
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int ret;
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ret = sunxi_init_platform_r_twi(socid, is_using_rsb());
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if (ret) {
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INFO("Could not init platform bus: %d\n", ret);
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pmic = UNKNOWN;
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return ret;
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}
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if (is_using_rsb()) {
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ret = rsb_init(rsb_hw_addr);
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if (ret) {
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pmic = UNKNOWN;
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return ret;
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}
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} else {
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/* initialise mi2cv driver */
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i2c_init((void *)SUNXI_R_I2C_BASE);
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}
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return 0;
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}
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int sunxi_pmic_setup(uint16_t socid, const void *fdt)
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{
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int ret;
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int node, parent, ret;
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uint32_t reg;
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INFO("PMIC: Probing AXP305 on RSB\n");
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node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp806");
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if (node >= 0) {
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pmic = AXP305;
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}
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ret = sunxi_init_platform_r_twi(socid, true);
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if (pmic == UNKNOWN) {
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node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp313a");
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if (node >= 0) {
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pmic = AXP313;
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}
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}
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if (pmic == UNKNOWN) {
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node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp717");
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if (node >= 0) {
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pmic = AXP717;
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}
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}
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if (pmic == UNKNOWN) {
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INFO("PMIC: No known PMIC in DT, skipping setup.\n");
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return -ENODEV;
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}
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if (fdt_read_uint32(fdt, node, "reg", ®)) {
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ERROR("PMIC: PMIC DT node does not contain reg property.\n");
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return -EINVAL;
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}
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pmic_bus_addr = reg;
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parent = fdt_parent_offset(fdt, node);
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ret = fdt_node_check_compatible(fdt, parent, "allwinner,sun8i-a23-rsb");
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if (ret == 0) {
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rsb_rt_addr = get_rsb_rt_address(pmic_bus_addr);
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if (rsb_rt_addr == 0) {
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ERROR("PMIC: no mapping for RSB address 0x%x\n",
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pmic_bus_addr);
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return -EINVAL;
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}
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}
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INFO("Probing for PMIC on %s:\n", is_using_rsb() ? "RSB" : "I2C");
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ret = pmic_bus_init(socid, pmic_bus_addr);
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if (ret) {
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INFO("Could not init platform bus: %d\n", ret);
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return ret;
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}
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ret = rsb_init();
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if (ret) {
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INFO("Could not init RSB: %d\n", ret);
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return ret;
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ret = axp_read(0x03);
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switch (ret & 0xcf) {
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case 0x40: /* AXP305 */
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if (pmic == AXP305) {
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INFO("PMIC: found AXP305, setting up regulators\n");
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axp_setup_regulators(fdt);
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} else {
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pmic = UNKNOWN;
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}
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break;
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case 0x48: /* AXP1530 */
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case 0x4b: /* AXP313A */
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case 0x4c: /* AXP313B */
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if (pmic == AXP313) {
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INFO("PMIC: found AXP313\n");
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/* no regulators to set up */
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} else {
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pmic = UNKNOWN;
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}
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break;
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case 0xcf: /* version reg not implemented on AXP717 */
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if (pmic == AXP717) {
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INFO("PMIC: found AXP717\n");
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/* no regulators to set up, U-Boot takes care of this */
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} else {
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pmic = UNKNOWN;
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}
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break;
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}
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pmic = AXP305;
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axp_setup_regulators(fdt);
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if (is_using_rsb()) {
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/* Switch the PMIC back to I2C mode. */
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return rsb_write(rsb_rt_addr, AXP20X_MODE_REG, AXP20X_MODE_I2C);
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}
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/* Switch the PMIC back to I2C mode. */
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ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
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if (ret)
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return ret;
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if (pmic == UNKNOWN) {
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INFO("Incompatible or unknown PMIC found.\n");
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return -ENODEV;
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}
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return 0;
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}
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void sunxi_power_down(void)
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{
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int ret;
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if (pmic == UNKNOWN) {
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return;
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}
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/* Re-initialise after rich OS might have used it. */
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ret = pmic_bus_init(SUNXI_SOC_H616, pmic_bus_addr);
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if (ret) {
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return;
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}
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switch (pmic) {
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case AXP305:
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/* Re-initialise after rich OS might have used it. */
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sunxi_init_platform_r_twi(SUNXI_SOC_H616, true);
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rsb_init();
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axp_power_off();
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axp_setbits(0x32, BIT(7));
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break;
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case AXP313:
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axp_setbits(0x1a, BIT(7));
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break;
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case AXP717:
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axp_setbits(0x27, BIT(0));
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break;
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default:
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break;
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