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Merge changes from topic "us_dsu_pmu" into integration

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* changes:
  feat(tc): enable Last-level cache (LLC)
  feat(cpus): add sysreg_bitfield_insert_from_gpr macro
  feat(tc): add DSU PMU node for tc3
  feat(tc): enable el1 access to DSU PMU registers
  style(tc): remove comment for plat_reset_handler
  fix(context-mgmt): keep actlr_el2 value in the init context
This commit is contained in:
Manish V Badarkhe 2024-07-24 16:07:55 +02:00 • committed by TrustedFirmware Code Review
commit 80da826429
8 changed files with 76 additions and 6 deletions
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5
fdts/tc3.dts
View file

@ -92,6 +92,11 @@
reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
};
dsu-pmu {
compatible = "arm,dsu-pmu";
cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";

3
include/lib/cpus/aarch64/cortex_a520.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -15,6 +15,7 @@
#define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_A520_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT U(0)
/*******************************************************************************
* CPU Auxiliary Control register 1 specific definitions.

1
include/lib/cpus/aarch64/cortex_a725.h
View file

@ -13,6 +13,7 @@
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_A725_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A725_CPUECTLR_EL1_EXTLLC_BIT U(0)
/*******************************************************************************
* CPU Power Control register specific definitions

1
include/lib/cpus/aarch64/cortex_x925.h
View file

@ -13,6 +13,7 @@
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_X925_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_X925_CPUECTLR_EL1_EXTLLC_BIT U(0)
/*******************************************************************************
* CPU Power Control register specific definitions

10
include/lib/cpus/aarch64/cpu_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -456,6 +456,14 @@
msr \_reg, x0
.endm
.macro sysreg_bitfield_insert_from_gpr _reg:req, _gpr:req, _lsb:req, _width:req
/* Source value in register for BFI */
mov x1, \_gpr
mrs x0, \_reg
bfi x0, x1, #\_lsb, #\_width
msr \_reg, x0
.endm
/*
* Apply erratum
*

6
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -335,6 +335,12 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e
u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val);
/*
* The actlr_el2 register can be initialized in platform's reset handler
* and it may contain access control bits (e.g. CLUSTERPMUEN bit).
*/
write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2());
#endif /* CTX_INCLUDE_EL2_REGS */
/* Start with a clean SCR_EL3 copy as all relevant values are set */

16
plat/arm/board/tc/include/platform_def.h
View file

@ -7,6 +7,7 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <cortex_a520.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/arm/board/common/board_css_def.h>
@ -446,6 +447,21 @@
#define SLC_DONT_ALLOC 0
#define SLC_ALWAYS_ALLOC 1
#define SLC_ALLOC_BUS_SIGNAL_ATTR 2
#define MCN_CONFIG_OFFSET 0x204
#define MCN_CONFIG_ADDR (MCN_BASE_ADDR + MCN_CONFIG_OFFSET)
#define MCN_CONFIG_SLC_PRESENT_BIT 3
/*
* TC3 CPUs have the same definitions for:
* CORTEX_{A520|A725|X925}_CPUECTLR_EL1
* CORTEX_{A520|A725|X925}_CPUECTLR_EL1_EXTLLC_BIT
* Define the common macros for easier using.
*/
#define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1
#define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT
#endif /* TARGET_PLATFORM == 3 */
#define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12)
#endif /* PLATFORM_DEF_H */

40
plat/arm/board/tc/include/tc_helpers.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,6 +9,9 @@
#include <platform_def.h>
#include <cpu_macros.S>
#define TC_HANDLER(rev) plat_reset_handler_tc##rev
#define PLAT_RESET_HANDLER(rev) TC_HANDLER(rev)
.globl plat_arm_calc_core_pos
.globl plat_reset_handler
@ -49,13 +52,42 @@ func plat_arm_calc_core_pos
ret
endfunc plat_arm_calc_core_pos
func mark_extllc_presence
#ifdef MCN_CONFIG_ADDR
mov_imm x0, (MCN_CONFIG_ADDR)
ldr w1, [x0]
ubfx x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1
sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, \
CPUECTLR_EL1_EXTLLC_BIT, 1
#endif
ret
endfunc mark_extllc_presence
func enable_dsu_pmu_el1_access
sysreg_bit_set actlr_el2, CPUACTLR_CLUSTERPMUEN
sysreg_bit_set actlr_el3, CPUACTLR_CLUSTERPMUEN
ret
endfunc enable_dsu_pmu_el1_access
func TC_HANDLER(2)
ret
endfunc TC_HANDLER(2)
func TC_HANDLER(3)
mov x9, lr
bl mark_extllc_presence
bl enable_dsu_pmu_el1_access
mov lr, x9
ret
endfunc TC_HANDLER(3)
/* -----------------------------------------------------
* void plat_reset_handler(void);
*
* Determine the CPU MIDR and disable power down bit for
* that CPU.
* -----------------------------------------------------
*/
func plat_reset_handler
mov x8, lr
bl PLAT_RESET_HANDLER(TARGET_PLATFORM)
mov lr, x8
ret
endfunc plat_reset_handler