Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.
Change-Id: I8a29a2c5b1a829db0c396407c3517c9e66caaa93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
These objects are needed to allow early enablement of the A53 core
clock.
Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add implementation for ARM PLL divider rate set mechanism.
Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add implementation for ARM PLL rate set mechanism.
Change-Id: Ic859567bd67747f173d425158cdc581801f7446c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID macro does not match the definition
in RSE. A paired macro, TFM_CRYPTO_EXPORT_PUBLIC_KEY, in the RSE's
header (located in interface/include/tfm_crypto_defs.h) is defined as
0x206. This causes the TF-A test PLATFORM_TEST=rse-rotpk to fail.
Correct the definition of RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID to make the
test pass.
Change-Id: I0bc24ed6dd23f2718e1edea5ec464545dab06983
Signed-off-by: Leo Yan <leo.yan@arm.com>
The MC_CGM1 clock objects will participate in A53 clocking.
Change-Id: I7309b630d72ac0ad66df7c299b678454220e0581
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
On S32CC SoCs, the set_parent operation will be used on clock modules
that are mux instances in order to establish the clock source. This will
be used for PLLs and MC_CGM muxes.
Change-Id: I7228d379500ea790459b858da8fc0bdcbed4fd62
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add all the clock objects needed to describe the ARM PLL, which can be
powered by either FXOSC or FIRC oscillators.
Change-Id: I2585ed38178ca1d5c5485adb38af1b3b8d94f1f6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The target_locality attribute is meant to specify that
a certain SW component is expected to run and thereby
send DPE commands from a given security domain. The DPE
service must be capable of determining the locality of
a client on his own. RSE determines the client's locality
based on the MHU channel used for communication.
If the expected locality (specified by the parent component)
is not matching with the determined locality by DPE
service then command fails.
The goal is to protect against spoofing when a
context_handle is stolen and used by a component
that should not have access.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I96d255de231611cfed10eef4335a47b91c2c94de
s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and Linflex clocks. For now, it will only contain the
frequency set for FXOSC. More clock management will be added in the next
commits.
Change-Id: Ie85465884de02f5082185f91749f190f40249c2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The set_rate callback will now be applied to FIRC, FXOSC, and SIRC
oscillators. It is a prerequisite for the upcoming commits that will
utilize this capability.
Change-Id: I82d1545c63b3e15497c1c002ff9ec0d7bf990aa0
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The oscillator clock objects will be used to describe the FIRC, FXOSC,
and SIRC clocks, all of which are oscillators on S32CC SoCs.
Change-Id: Icf235cc9b8f1d95d2c0051ce9a7655fd120289b8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The clock IDs are organized into categories, which are determined based
on the first 2 MSB bits for each ID. Currently, there are two big
categories: hardware and software-defined clocks.
The first category refers to clock IDs understood by the S32CC PLL muxes
and MC_CGM module muxes and is immutable. The last category of the
clocks includes software-defined IDs for clocks to allow an easy
representation of the hierarchy.
Change-Id: Idc079feb3ca5f92d8bf337ef09efad006e267088
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.
Change-Id: I6ba2173e73222269a2dfca4c6897229276a150c0
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Fix some clocks and reset binding values.
Change-Id: Ibe480aa77cd0abb63d08bbee08ad4ec9d5d2a397
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Add the system reset management into the stm32mp
reset driver.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I748f10de2398e1323160f479f99e92abd2f65dca
Rename GENMASK parameters for better readability to avoid
misinterpreting the 'l' as '1' in BIT(l) usage.
Change-Id: I9a85c750607e098939d70c61c2e29f4788b99016
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Redefine GENMASK_32 and GENMASK_64 to avoid the impact of CWE-190, which
applies due to (~0 << (l)) syntax, where a wraparound occurs.
Change-Id: I8d08911664db7052351312d310566bb546dfb486
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
MISRA interprets all unsigned integer literals as UTLR, which has the
lowest rank required to represent a value. In this specific case, the
value 1U was interpreted as an unsigned char. As a result, explicit
casts are necessary to avoid issues with MISRA 12.2.
Change-Id: I4c1231ffabb27442c6a48dabd96942574d27c719
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
BIT_32 macro is already defined as part of the utils_def.h and included
through mmc.h
Suggested-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7921681ee9af7d65e8eab5a0bf1d5236ecfed1a4
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Currently MDCR_EL3 register value is same for all the
worlds(Non-secure, Secure, Realm and Root).
With this approach, features enable/disable settings
remain same across all the worlds. This is not ideal as
there must be flexibility in controlling feature as per
the requirements for individual world.
The patch addresses this by providing MDCR_EL3 a per world
value. Features with identical values for all the worlds are
grouped under ``manage_extensions_common`` API.
Change-Id: Ibc068d985fe165d8cb6d0ffb84119bffd743b3d1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
The ARMv8 ARM J.a describes the ID_AA64DFR0_EL1.PMUver field as allowing
a maximum version number of 8 now. The added features extend the Common
event number space and clarify on some UNPREDICTABLE behaviour.
None of this affects TF-A or any system registers, so just increase the
maximum known version number to let the FEATURE_DETECTION test pass on
ARMv8.8 implementations.
Change-Id: Icab48630c1635bcd78a710b443f0db01b8ff7c9b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This callback will be used to set a clock's rate if the underlying clock
driver supports this option. The function's last parameter is an output
parameter, storing the actual frequency set by the clock driver, as it
may not precisely match the requested rate in some cases.
Change-Id: I6a399bf6f64407d5fbff36407561e4bf18104cf1
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This callback will be used to set a clock's parent if the underlying
clock driver supports this option.
Change-Id: Ie8a77d17dd3cc867bd520217b481cd188317a9c9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* changes:
fix(st-gpio): configure each GPIO mux as secure for STM32MP2
feat(st-gpio): add set GPIO config API
fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value
refactor(st): use GPIO banks definition from bindings
feat(dt-bindings): describe ST GPIO banks and config
Add get and set GPIO level from bank and pin value.
Add functions to set a pad in GPIO configuration
and to apply some settings.
Change-Id: I5e3acb5c95cd03f3e130e1a263b221b956cb3c8d
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Describe GPIO banks configs so that it can be used in
an STM32MP device-tree file.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: If5dd05aae314cbb3189eb02c9fe555b832ac2bdb
Most newer CPU's have DSU and CPU power control core-off bit which
means before turning off CPUs from base power controller we need to
turn individual cores off from CPU Power control.
However there are certain older CPU's that don't have DSU and
don't support CPUPWRCTRL_EL1, so populate them as a list
and ignore setting core-off bit for those older CPU's as all newer
CPU's have them.
Note: unfortunately there is no mechanism to identify if a DSU is
present and CPUPWRCTRL_EL1 is supported through any CPU control
registers and CPUPWRCTRL_EL1 is supported only for ARM64 platforms
and not available in ARM32 platforms.
Change-Id: Iba6c3c8db60dbeb177cead7ebc65df8265860da7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct
feat(stm32mp1-fdts): remove RTC clock configuration
refactor(st-clock): move stm32mp1_clk_rcc_regs_*lock
refactor(st-clock): driver size optimization
refactor(st-clock): remove BL32 support on STM32MP13
feat(st-clock): don't gate/ungate an oscillator if it is not wired
feat(dt-bindings): add missing SPIx bus clocks
feat(stm32mp1-fdts): remove PLL1 settings
feat(st-clock): update with new bindings
feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1
feat(dt-bindings): new RCC DT bindings
feat(stm32mp1): always boot at 650MHz
refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13
fix(st-clock): display proper PLL number for STM32MP13
fix(st-clock): do not reconfigure LSE
feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation
refactor(st-clock): remove unused clk function in API
refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config
feat(st-clock): add function to restore generic timer rate
Improve the restart handling of DPE. In the case of a restart
scenario where only that core is restarted which executes
the DPE client, but the core executes the DPE service
remains up and running. In this case, client needs to save
a valid context handle to be able to send commands again
to the DPE service during the new boot sequence.
BL1 saves a valid parent context handle to SDS
before passing the execution to BL2. This handle
can be used in case of a restart scenario when AP
is restarted but RSE is not. Because in that case
RSE does not save an initial context handle to SDS,
which meant to be used by AP during the boot process.
By then the very first initial context handle is
invalidated because it was already used in the
previous boot cycle by BL1.
BL2 does not need to do this, because the cold
boot starts with BL1.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Id14eefd2ec758f89f672af176e4f5386a397fa35
* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch attestation key and token from RSE
feat(psa): introduce generic library for CCA attestation
feat(rdfremont): initialize the rse comms driver
feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3
fix(rse): include lib-psa to resolve build
feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms
feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms
feat(rdfremont): initialize GPT on GPC SMMU block
feat(rdfremont): update Root registers page offset for SMMUv3
feat(rdfremont): enable MTE2 if present on the platform
feat(rdfremont): enable SVE for SWD and NS
feat(rdfremont): enable AMU if present on the platform
feat(rdfremont): enable MPAM if present on the platform
feat(rdfremont): add DRAM pas entries in pas table for multichip
feat(rdfremont): add implementation for GPT setup
feat(rdfremont): integrate DTS files for RD-Fremont variants
feat(rdfremont): add support for RD-Fremont-Cfg2
feat(rdfremont): add support for RD-Fremont-Cfg1
feat(rdfremont): add support for RD-Fremont
feat(neoverse-rd): add scope for RD-Fremont variants
feat(neoverse-rd): add multichip pas entries
feat(neoverse-rd): add pas definitions for third gen platforms
feat(neoverse-rd): add DRAM layout for third gen platforms
feat(neoverse-rd): add SRAM layout for third gen platforms
feat(neoverse-rd): add firmware definitions for third gen platforms
feat(neoverse-rd): add RoS definitions for third gen platforms
feat(neoverse-rd): add CSS definitions for third gen platforms
SCP_BL2 is part of CCA's TCB. The SCP_BL1 is loaded
by RSE. It has already added to the platform
attestation token. SCP_BL2 was missed, so it is
fixed now.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ic87743564136f03a901c90ff1ec614f5965b9a47
In case of load error, platform may need to try another instance, either
from another storage, or from the same storage in case of PSA FWU. On
MTD devices such as NAND, it is required to define backup partitions.
A new function plat_setup_try_img_ops() should be called by platform
code to register handlers (plat_try_images_ops) to manage loading
other images.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ideaecaf296c0037a26fb4e6680f33e507111378a
The plat_try_next_boot_source() API is not used by any upstream platform
and not used by platforms that asked for this API. It is then removed.
It will be replaced with a more generic interface in next patch.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I298c7acace8c5efb3c66422d8d9280ecd08e5ade
SPM-MM defines AP TZC-400 regions as such:
1: 0xff000000 0xffffffff S
2: 0x80000000 0xfeffffff NS
3: 0x880000000 0xfffffffff NS
4: 0xff600000 0xff60ffff NS
Region 4 (using filter 0) defines the SPM NS shared buffer between
normal world and secure world.
However region 4 overlaps with region 1 (using filter 0) defined as
secure.
It is forbidden to define overlapping regions beyond region 0 for the
same filter. This is reported as a violation in the TZC-400 controller.
With FVP models < 11.25 the error is latent but not reported to the PE
(reason for this behavior is unclear).
With greater FVP model version the error is reported as an asynchronous
external abort (SError exception).
By carving out the SPM NS shared region (with regions as defined below),
the violation is no longer reported and test passed with recent FVP
models:
1: 0x80000000 0xfeffffff NS
2: 0xff000000 0xff5fffff S
3: 0xff600000 0xff60ffff NS
4: 0xff610000 0xffffffff S
5: 0x880000000 0xfffffffff NS
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idc3370803ad204ac29efeded77305e52e17cc1c1
RCC bindings alignment with MP13 RCC bindings:
- merge of 'st,clksrc' and 'st,pkcs' nodes into 'st,clksrc'
- no ordering requirements on 'st,clksrc' node
- use DIV() macro for 'st,clkdiv' node
- no ordering requirements on 'st,clkdiv' node
- new pll binding
Change-Id: Id3ca30608dde2091145123512c42c6958a378d91
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Remove the unused functions in stm32mp clk API:
- stm32mp_stgen_get_counter (change to static, no more exported)
- stm32mp_stgen_restore_counter
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ib6ca72723eac3e133f1ca0dee504ef344c72e0bf
Add a function to restore the CPU generic timer rate from STGEN content.
After wake-up from LPLV-Stop2, STGEN content is not lost, but generic timer
has been reset.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I6f91dbd051f76383e9ff1d6bb86225d373dbf33a
