When RME is enabled on SBSA, the RMM is located at the start of the NS
RAM and the device tree after it. This patch adjust the DT memory start
address so that anyone reading it has an accurate view of the system
configuration.
Change-Id: I32ca63a78d68831faf2c65ad60a45c841b7cbada
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
When RME is enabled, (1) the RMM is installed at the base of system RAM,
(2) the base of the system RAM is shifted upward, after the RMM and (3)
the device tree is relocated to the new system RAM base.
This patch relocates the device tree to the new system RAM base before
the RMM is installed in RAM. From there, other accesses to the device
tree are using the new location.
Change-Id: I0cb4e060ca33a11becd78fe48fab4dc76f0b484b
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
When RME is enabled the RMM is placed at the bottom of the NS RAM,
meaning that NS_DRAM0_BASE has to be located after that.
This patch disscociates the base of the NS RAM as defined by QEMU by
introducing a new define, PLAT_QEMU_DRAM0_BASE. An offset can be added
to that new define when the software's view of the base memory need to
differ from QEMU.
No change in functionality.
Change-Id: I887f9993d5a61896352cfff17e0d92e2c2b9030a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Following what was done for:
f465ac2210 ("fix(qemu): increase max FIP size")
increase the size of the FIP image to take up the remaining
space in FLASH0. That way the RMM image can also be added
to the FIP.
Change-Id: I89bba36f751468e99241f1c20b51c48fe06d8229
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Move all DT related functions to file sbsa_platform_dt.c so that clients
other than SIP SVC can use the funtionality. At the same time, make all
functions that don't need outside visibility static.
No change in functionality.
Change-Id: I9bce730c8f9e2b827937466f4432ecfa74c35675
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Creating accessor functions to access information held by struct
qemu_platform_info. That way the code that is relevant to fetching
information from the device tree can be taken out of sbsa_sip_svc.c and
placed in a file where other client can use the information it provides.
No change in functionality.
Change-Id: I989952ee6d15e1436549002dd7c7767c745ea297
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
There is no relation between the name of function sip_svc_init() and
what it does. As such rename it to something more appropriate and move
it to a header that make sense.
No change in functionality.
Change-Id: I7bd78b1fe70e2930c395ef0a097bfad3b1e55d3a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Move structure declaration related to the DT to their own header. That
way they can be reused by other files. At the same time, typedefs are
removed and structure names prepended with "platform_" to avoid clashing
with other structure declarations available in the system.
No change in functionality.
Change-Id: If67a141cc7441b0636af774d7edfe51cf8034a11
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Rename struct dynamic_platform_info to qemu_platform_info and properly
declare a variable name "dynamic_platform_info". That way structures
related to the device tree can be moved out of sbsa_sip_svc.c.
No change in functionality.
Change-Id: I1af39047af96ae02f3b8eecda6cb67508f14d37a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Add a new parameter to make the size of the L0GPT configurable based on
the amount of memory available on a platform. That way platform with a
wider physical address range can be supported.
No change in functionality.
Change-Id: I5b7b4968636d61929ad6ebdc05c389291cf510b1
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Some platforms such as QEMU-SBSA access the device tree located at the
bottom of the non-secure RAM from BL31. When GPT checks are enabled at
BL2, that access generates a GPT check fault because the device tree
area is configure as non-secure RAM and the access is made from secure
EL3.
We could change the device tree memory area configuration in a way that
it is accessible from BL31, but that would require another configuration
of the GPT before going to BL33.
Since BL2 and BL31 are both running at EL3, a better solution is simply
move the GPT configuration and enabling to BL31, after the device tree
has been probed.
No change in functionality.
Change-Id: Ifa01c50164268b993d563c32e4e42140259c44e2
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
[Added changelog description]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
When building SBSA, using DT functions from fdt_wrappers.c produces a
linker error. Adding:
BL2_SOURCES += ${FDT_WRAPPERS_SOURCES}
fixes the problem. Since the same inclusion would be present in both
qemu/platform.mk and qemu_sbsa/platform.mk, do the changes in
qemu/common/common.mk.
Change-Id: I775b06c1741f6618813c5e1d2c64cdc1888d8519
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
To produce PHIT HOB list in FVP, add build path for hob library.
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I8f4905433bd1cc6f4c9247197b9bd69041f50fd7
According to Platform Initialization (PI) Specification [1] and
discussion on edk2 mailing list [2],
StandaloneMm shouldn't create Hob but it should be passed from TF-A.
IOW, TF-A should pass boot information via HOB list to initialise
StandaloneMm properly.
And this HOB lists could be delivered via
- SPM_MM: Transfer List according to the firmware handoff spec[3]
- FF-A v1.1 >= : FF-A boot protocol.
This patch introduces a TF-A HOB creation library and
some of definitions which StandaloneMm requires to boot.
Link: https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf [1]
Link: https://edk2.groups.io/g/devel/topic/103675962#114283 [2]
Link: https://github.com/FirmwareHandoff/firmware_handoff [3]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I5e0838adce487110206998a8b79bc3adca922cec
According to Platform Initialization (PI) Specification [1] and
Discussion on edk2 mailing list [2],
StandaloneMm shouldn't create Hob but it should be passed from TF-A.
IOW, TF-A should pass boot information via PHIT Hob to initialize
StandaloneMm properly.
This patch modifies Hob creation code from edk2 codebase
so that TF-A could create Hob information properly to boot StandaloneMm
Link: https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf [1]
Link: https://edk2.groups.io/g/devel/topic/103675962#114283 [2]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I5e427b620d8006b118b266370bd08d4b0ff56a83
The ROMLIB build currently has a strong dependency on MbedTLS. This
patch has been introduced to remove this dependency, making it more
flexible.
Change-Id: If8c4cc7cf557687f40b235a4b8f931cfb70943fd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Remove the unused jmptbl.i file. The ROMLIB Makefile expects
platforms to provide the jmptbl according to their requirements.
Change-Id: I2784eaca5061aa77fdd99f7b2b5ef5a1145475e9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")
To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.
We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d
Add basic CPU library code to support the Alto CPU.
Change-Id: I45958be99c4a350a32a9e511d3705fb568b97236
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>
This patch enable support for loading FIP image into DRAM rather than
flash drive.
Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Currently the FPGA reconfig status only return a single error status
which make the debugging of FPGA reconfiguration hard.
This patch is to expose the error status, major error code and
minor error code, for the FPGA reconfig to upper layer app.
Change-Id: I2fc68e30b45ff137f3e52f9569fdf2eaf2ca94ee
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Fix issues in RD1-AE flattened device tree source
- Update GIC GICR register region size to 0x40_0000.
GICR region size = 16 (RDcount) * 64KB frame size * 4 (with GIC v4.1)
- Update cpu_on function ID in psci node.
Use SMC64 version function ID 0xc4000003 instead. Although this
property doesn't actually take effect, align its value with
cpu_suspend selection to avoid any confusion.
Change-Id: Ib0840db45d32f0c8f1eb7dc74dc7d9b4ca6de0c3
Signed-off-by: David Hu <david.hu2@arm.com>
It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.
Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib416c89226475d44746a7561dd949a14349c3e4b
- MT8196 has 271 GPIO pins. Therefore, update id to a proper datatype.
- Add GPIO support for MT8196.
Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Change-Id: I283939684b54f79d1bba02f38e047e756a56f0c9
Previously we only enabled 8GB unless we were loading the filesystem
from RAM.
Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Add a node for AP_REFCLK Non-Secure Generic Timer in device tree, which
acts as a system timer to fix the failure of SystemReady IR ACS BSA
test case 402.
Refer to https://github.com/ARM-software/bsa-acs/blob/v23.09_REL1.0.6\
/docs/arm_bsa_testcase_checklist.rst?plain=1#L115
for more information.
Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Change-Id: I3e63a5ecfd8c6211f917ca3844b8b7bda208d83a
Update the boot sequence in the RD-1 AE documentation
to include BL32 (OP-TEE).
Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Change-Id: I25fdc114bb71d3ad7e1bb2d845f758d6af037e3d
This is a small change to the behaviour of the `MAKE_DEP` macro to force
it to take its inputs as arguments, rather than assuming the variables
that its inputs come from.
Change-Id: Ibe44f19e6bea43c9feed34710cdd30704576b4d7
Signed-off-by: Chris Kay <chris.kay@arm.com>
This change centralises the logic that disables the default suffix rules
that Make provides. These rules are a hold-over from legacy standards of
Make, and occasionally conflict with our rules.
Change-Id: I9e023edbc01b5ae48a96fa1078d0b81faabb0cb9
Signed-off-by: Chris Kay <chris.kay@arm.com>
This change modifies the build rules for static libraries so that
individual rules which use those libraries depend directly on the
archive files that are generated, rather than their phony target aliases
and `-lX` link flags.
The goal of this is to clean up Make's view of the dependencies between
files, avoiding phony targets (which do not honour timestamps) making
their way into intermediate dependencies.
Change-Id: I96d655fcd94dc259ffa6e8970b2be7b8c7e11123
Signed-off-by: Chris Kay <chris.kay@arm.com>
