Commit graph

15926 commits

Author SHA1 Message Date
Manish V Badarkhe
63d2020f57 fix(drtm): adjust Event Log size in DLME
Updated the code to ensure the Event Log in the DLME meets
the minimum size requirement of 64KB, as specified in the
specification.

Change-Id: If0b179a97c0dca489edc0047da401bbb4ce09f39
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2024-12-16 09:33:02 +00:00
Manish V Badarkhe
3c72b2ab0b Merge "fix(tc): eliminate unneeded MbedTLS dependency" into integration 2024-12-16 09:32:16 +01:00
Manish V Badarkhe
22220e69f9 fix(tc): eliminate unneeded MbedTLS dependency
The rse_platform_api.h file includes certain MbedTLS headers,
introducing an unnecessary dependency when building the TC
platform with RSE support unconditionally.
However, these headers are not required, as the BL31
implementation only initializes RSE communication,
which does not rely on MbedTLS.

Change-Id: If45122aaf158be128f8978422fd870dbb0a0d090
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2024-12-16 09:25:09 +01:00
Xiangzhi Tang
a1763ae97e feat(mediatek): add vcp driver support
It is excepted that kernel vcp can request the vcp hw do
some security setting via SMC call services.

Signed-off-by: Xiangzhi Tang <xiangzhi.tang@mediatek.corp-partner.google.com>
Change-Id: Ib5c01c1d72b3483262dcd821878e6e53ba9c681c
2024-12-16 07:17:23 +01:00
Manish V Badarkhe
9ac687f7be Merge changes from topic "hf_transfer_list" into integration
* changes:
  fix(tlc): pass the flags from client interface
  fix(tlc): relax entry addition from YAML files
  feat(tlc): add --align argument
  fix(tlc): add void entries to align data
  fix(handoff): correct 8-bit modulo csum calculation
  feat(tlc): formalise random generation of TEs
2024-12-13 18:31:26 +01:00
Manish Pandey
cb4562e05e Merge changes from topic "clang-rockchip" into integration
* changes:
  build(rk3399): m0: Makefile: respect verbosity for linkerfile
  build(rk3399): m0: fail linker and assembler on warnings
  build(rk3399): m0: remove redundant M0_CROSS_COMPILE
  feat(build): rk3399: m0: add support for new binutils versions
  fix(rk3399): m0: Makefile: fix outside array bounds warning
  refactor(rk3399): m0: Makefile: use same tools as in build_macros.mk
  refactor(rk3399): m0: Makefile: specify ARCH to be rk3399-m0
  fix(rk3588): pmu: fix assembly symbol redefinition
  fix(rockchip): pmu: Do not mark already defined functions as weak
  fix(rk3399): dram: Fix build with gcc 11
  fix(rk3288): remove unused function
  fix(px30): remove unused function
2024-12-13 17:36:10 +01:00
Valentin Caron
33573ea684 fix(stm32mp1-fdts): re-enable RTC clock
On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
yet. Re-enable it temporary to get LSE as clock source of RTC.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Change-Id: Ib6071229552e456faffb4fdfc8db9808140d54a7
2024-12-13 16:54:37 +01:00
Manish Pandey
31a223cbb1 Merge "feat(tc): add devicetree node for AP/RSE MHU" into integration 2024-12-13 14:30:08 +01:00
Manish V Badarkhe
62ed5aa0b6 Merge "fix(romlib): romlib build without MbedTLS" into integration 2024-12-13 12:16:47 +01:00
Manish V Badarkhe
4817b85d72 Merge "feat(tc): initialize MHU channels with RSE" into integration 2024-12-13 11:51:01 +01:00
Manish Pandey
1b2e12cc86 Merge "fix(tc): map mem_protect flash region" into integration 2024-12-13 11:50:39 +01:00
Gatien Chevallier
7f41506fa7 feat(stm32mp2): add a runtime service for STGEN configuration
Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Therefore, implement a SiP SMC handler for this purpose and
a runtime service to catch SIP SMCs.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I7854e1ae6328f149798b43d52bb1ecdf71a5aa69
2024-12-13 11:48:38 +01:00
Gatien Chevallier
f55b136abc feat(stm32mp2): add common SMC runtime services
Implement the common SMC runtime services for stm32mp2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I214e4b2bfba439572c079bbc9ffb62bc87793ce9
2024-12-13 11:48:37 +01:00
Yann Gautier
39b08bc366 feat(stm32mp1): rework SVC services
Having two generations of STM32MPX using the same SMCCC protocol,
rework the SVC services setup to put in common what can be put
in common and implement platform-specific handlers.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I000573e50d55dc70163c2657c12cc84085416f6b
2024-12-13 11:48:29 +01:00
Manish Pandey
d7ad23796c Merge changes Ib1b810df,I5492bab5 into integration
* changes:
  feat(tc): add dsu pmu node for TC4
  feat(tc): enable DSU PMU el1 access for TC4
2024-12-13 11:46:45 +01:00
Manish V Badarkhe
f3ad3f48c2 Merge "feat(qti): platform support for qcs615" into integration 2024-12-13 11:30:50 +01:00
quic_assethi
f60617d3b1 feat(qti): platform support for qcs615
Change-Id: Ibbe78a196d77530fa9d94d7d12b2f08a4b66d62e
Signed-off-by: Amarinder Singh Sethi <quic_assethi@quicinc.com>
2024-12-13 14:54:22 +05:30
Manish Pandey
f8872c9440 Merge "fix(cpus): workaround for Cortex-X4 erratum 2923985" into integration 2024-12-12 22:43:22 +01:00
Manish Pandey
45db86e0d4 Merge "feat(fpmr): disable FPMR trap" into integration 2024-12-12 22:42:20 +01:00
Arvind Ram Prakash
a57e18e433 feat(fpmr): disable FPMR trap
This patch enables support of FEAT_FPMR by enabling access
to FPMR register. It achieves it by setting the EnFPM bit of
SCR_EL3. This feature is currently enabled for NS world only.

Reference:
https://developer.arm.com/documentation/109697/2024_09/
Feature-descriptions/The-Armv9-5-architecture-extension?lang=en

Change-Id: I580c409b9b22f8ead0737502280fb9093a3d5dd2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
2024-12-12 10:03:23 -06:00
J-Alves
537a25ef7f fix(tlc): pass the flags from client interface
Provide the 'flags' from the arguments of the create
command to the TransferList __init__ function.

This is so that the '--flags' argument to the tool is actually
used.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic3f548e0ce7e704b3a12c2908f03d6a639bfa6f0
2024-12-12 16:12:35 +02:00
Yu Shihai
06fa4c4df2 feat(tc): add devicetree node for AP/RSE MHU
These dts nodes are used by u-boot MHU/RSE driver to faciliate
communication with RSE over MHU.

FPGA doesn't seem to have the MHU instances which are used to
communicate with RSE so keep rse mhu disabled for fpga.

Signed-off-by: Yu Shihai <yu.shihai@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib10b3da09626e5beb6d6cd87b1618a143234a5d0
2024-12-12 10:58:20 +00:00
Ryan Everett
52d2934560 fix(psa): increase psa-mbedtls heap size for rsa
The value assigned for the mbedtls heap size for large
rsa keys was too small when PSA_CRYPTO is set to 1,
leading to run-time failures if one was to attempt
to use a large RSA key with PSA_CRYPTO=1.

Change-Id: Id9b2648ae911879f483f1b88301f28694af0721d
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
2024-12-12 10:13:41 +00:00
Arvind Ram Prakash
cc46166144 fix(cpus): workaround for Cortex-X4 erratum 2923985
Cortex-X4 erratum 2923935 is a Cat B erratum that applies
to all revisions <= r0p1 and is fixed in r0p2.

The workaround is to set CPUACTLR4_EL1[11:10] to 0b11.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9207802ad479919a7f77c1271019fa2479e076ee
2024-12-11 16:09:20 -06:00
Manish V Badarkhe
e372c29153 Merge "chore(romlib): remove unused jmptbl.i file" into integration 2024-12-11 19:01:29 +01:00
Mark Dykes
255d907675 Merge "feat(intel): add support for query SDM config error and status" into integration 2024-12-11 17:53:12 +01:00
Yann Gautier
7640df6f1e fix(encrypt-fw): put build_msg under LOG_LEVEL flag
In tools directory, contrary to other parts of TF-A code,
LOG_LEVEL_NOTICE is 20, and LOG_LEVEL_ERROR is 10. If LOG_LEVEL is
set to 10, which is the case if BUILD_INFO=0, then we can have this
compilation warning:
src/main.c:29:19: warning: ‘build_msg’ defined but not used
 [-Wunused-const-variable=]
   29 | static const char build_msg[] = "Built : " __TIME__ ",
 " __DATE__;
      |                   ^~~~~~~~~

Avoid that by putting it under '#if LOG_LEVEL >= LOG_LEVEL_NOTICE'.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic724610d6df811fc889775dbd361087e0958d31e
2024-12-11 15:59:22 +01:00
Manish V Badarkhe
7dc43344c4 Merge changes from topic "update-mbedtls-to-3.6.2" into integration
* changes:
  feat(mbedtls): mbedtls config update for v3.6.2
  docs(prerequisites): update mbedtls to version 3.6.2
  refactor(mbedtls): rename default mbedtls confs
2024-12-11 14:55:43 +01:00
Jackson Cooper-Driver
4bfe49ec4e fix(tc): map mem_protect flash region
TC platform was missing this region's mapping in its plat_arm_mmap
structure causing a data abort when trying to access it.

Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I0a6322685f1ee017b0f0cfa795abac0524c13287
2024-12-11 10:55:20 +00:00
Leo Yan
0328f34222 feat(tc): initialize MHU channels with RSE
Initialize MHU channels between TF-A and RSE, this is a preparation
for later sending messages to RSE.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I66095cafcc1d48249cf957a49dc1dad3059a0010
2024-12-11 10:42:52 +00:00
Boyan Karatotev
4557c0c001 fix(docs): put INIT_UNUSED_NS_EL2 docs back
Commit b65dfe40a removed the documentation for this flag in error. Put
it back.

Change-Id: I61a352553a010385997c47116b53d2fbe939ccd4
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
2024-12-11 09:17:32 +00:00
Jagdish Gediya
50ad0cfda3 feat(tc): add dsu pmu node for TC4
Add DSU PMU node for TC4. DSU PMU interrupt is not connected on TC3
but it is connected on IRQ 290 on TC4, so add interrupt property
specifically for TC4.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib1b810df65004987e9f3cf1bbd5deb5d211f3a17
2024-12-10 17:11:40 +00:00
Jagdish Gediya
00397b30b8 feat(tc): enable DSU PMU el1 access for TC4
Enable DSU PMU EL1 access for TC4 to use DSU PMU using perf
in Linux.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I5492bab5c95d60ffaaede4606d8d75c00f988eb6
2024-12-10 16:12:59 +00:00
Mac Shen
3e43d1d317 feat(mt8196): enable DP and eDP for mt8196
- Add register definitions for DP
- Add mmap entry for DP register access

Change-Id: I22ed9fa36a7e13fcaed0c137d0e8f4449b6a52d7
Signed-off-by: Mac Shen <mac.shen@mediatek.com>
2024-12-10 10:25:01 +02:00
Harrison Mutai
f0e15ddca3 fix(tlc): relax entry addition from YAML files
Relax entry addition from YAML files to allow the addition of
entries not known to the tool. It is not possible to keep track of
every possible TE, and a user might want to add an entry that hasn't
yet been specified.

Change-Id: Ib5d227bc41cd3dd8b530699c1bab3165a3114a3c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-12-09 18:21:11 +00:00
J-Alves
c4c8e26a69 feat(tlc): add --align argument
Extended the command line interface to receive an alignment
argument.

TLC tool will align the data of the TEs accordingly.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I281b0b4c1851d58377bf6b31fcee03ee2f53367b
2024-12-09 18:21:11 +00:00
J-Alves
03c2660f75 fix(tlc): add void entries to align data
Add void entries to ensure proper alignment of data in the TL,
addressing runtime errors caused by previously unaccounted padding bytes
between TE's.

Change-Id: Id2acee8f4df0dcc52eedc4372b962a51acb9d8ce
Signed-off-by: J-Alves <joao.alves@arm.com>
Co-authored-by:: Harrison Mutai <harrison.mutai@arm.com>
2024-12-09 18:21:11 +00:00
Harrison Mutai
5ca0241c7a fix(handoff): correct 8-bit modulo csum calculation
Fix the handoff 8-bit modulo checksum calculation to ensure we never get
a checksum larger than 8 bits. The previous calculation failed to
truncate the sum at the final step in update_checksum

Change-Id: Ice0b72eb139af90f416adeff157d337646d6201a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-12-09 18:21:11 +00:00
Harrison Mutai
157c619786 feat(tlc): formalise random generation of TEs
To facillitate our testing, add some fixtures to make it easier to
generate transfer entry data.

Change-Id: Ieb76e54e69f410f4f7e1b55fc2cff282e592d1a4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-12-09 18:21:11 +00:00
Ryan Everett
c307efce85 feat(mbedtls): mbedtls config update for v3.6.2
This new update to the LTS branch of MbedTLS provides
the fix for a buffer underrun vulnerability. TF-A does
not use the previously vulnerable functions
`mbedtls_pk_write_key_der` or `mbedtls_pk_write_key_pem`.
Full patch notes to this MbedTLS update can be found at
https://github.com/Mbed-TLS/mbedtls/releases/tag/mbedtls-3.6.2.

We now enforce the mbedtls version to be greater than or equal
to 3.6.2 in our default configs.

Change-Id: I79027f6c741ab3f419f7b555321507e6a78b977b
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
2024-12-09 16:00:38 +00:00
Ryan Everett
95037029a7 docs(prerequisites): update mbedtls to version 3.6.2
This new update to the LTS branch of MbedTLS provides
the fix for a buffer underrun vulnerability. TF-A does
not use the previously vulnerable functions
`mbedtls_pk_write_key_der` or `mbedtls_pk_write_key_pem`.
Full patch notes to this MbedTLS update can be found at
https://github.com/Mbed-TLS/mbedtls/releases/tag/mbedtls-3.6.2.

Change-Id: Ibc4a8712c92019648fe0e75390cd3540d86b735d
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
2024-12-09 15:59:58 +00:00
Ryan Everett
640ba6343b refactor(mbedtls): rename default mbedtls confs
Change the name of these confs to be version agnostic,
we will later use these configs to enforce the mbedtls
minimum version

Change-Id: I1f665c2471877ecc833270c511749ff845046f10
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
2024-12-09 15:59:45 +00:00
Manish Pandey
ae952c1e51 Merge "docs(auth): extrapolate on the functions within a CM" into integration 2024-12-09 15:34:29 +01:00
Manish Pandey
8e5a872627 Merge changes from topic "hob_creation_in_tf_a" into integration
* changes:
  feat(fvp): build hob library
  feat(lib): introduce Hob creation library
  feat(lib): modify Hob creation code imported from edk2
  feat(lib): copy StandaloneMm Hob creation library in edk2
2024-12-09 15:29:48 +01:00
Ryan Everett
8edd6c6f45 docs(auth): extrapolate on the functions within a CM
Add descriptions for the various parameters for each
function.
Add more description to the example implementation.

Change-Id: I4b7a1ff38914d061e499c1b67e762a484688ee05
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
2024-12-09 14:00:33 +00:00
Olivier Deprez
faddccc43e Merge "fix(rd1ae): fix rd1-ae device tree" into integration 2024-12-09 12:12:01 +01:00
Manish V Badarkhe
5cc9bdd399 Merge "fix(cert-create): load openSSL configuration before PKCS11 operations" into integration 2024-12-09 11:40:49 +01:00
Mathieu Poirier
acb09373ba feat(qemu-sbsa): add support for RME on SBSA machine
Add the necessary foundation to support Arm's RME extension on the SBSA
reference architecture.

Change-Id: If5a63ed0015cb33fcae367ff2cded811bbdc1e54
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2024-12-06 11:20:43 -07:00
Mathieu Poirier
fb4edc35bc feat(qemu-sbsa): configure RMM manifest based on system RAM
The RMM manifest needs to reflect the amount of RAM available on the
system.  Since system RAM is based on user input and reflected in the
device tree, get the information from there rather than using hard coded
values.

Change-Id: I63f090c1c04d9addfcd7a349450735728fa88ed0
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2024-12-06 11:20:43 -07:00
Mathieu Poirier
d079d65d42 feat(qemu-sbsa): configure GPT based on system RAM
The amount of memory supported by the SBSA platform is dynamic
and dependent on user input.  Since the configuration of the GPT
needs to reflect the system memory, QEMU_PAS_NS0 needs to be set
based on the information found in the device tree.

Change-Id: I5d1411ac00020b7b38a652ba2904c8a70fa64d18
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2024-12-06 11:20:43 -07:00