Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-18 18:44:22 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge changes I52c84dc2,I9b2a2a11 into integration

Browse source 
* changes:
  fix(intel): add FPGA isolation trigger when reconfiguration
  fix(intel): redesign F2SOC bridge enable and disable flow for Agilex5
This commit is contained in:
Yann Gautier 2024-11-25 17:09:09 +01:00 • committed by TrustedFirmware Code Review
commit fe85aa7ef5
4 changed files with 145 additions and 122 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
plat/intel/soc/common/include/socfpga_mailbox.h
View file

@ -48,6 +48,7 @@
#define MBOX_CMD_GET_IDCODE 0x10
#define MBOX_CMD_GET_USERCODE 0x13
#define MBOX_CMD_GET_CHIPID 0x12
#define MBOX_CMD_FPGA_CONFIG_COMP 0x45
#define MBOX_CMD_REBOOT_HPS 0x47
/* Reconfiguration Commands */
@ -260,4 +261,6 @@ int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf);
int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len);
int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len);
int mailbox_send_fpga_config_comp(void);
#endif /* SOCFPGA_MBOX_H */

16
plat/intel/soc/common/soc/socfpga_mailbox.c
View file

@ -622,6 +622,22 @@ int mailbox_init(void)
return MBOX_RET_OK;
}
int mailbox_send_fpga_config_comp(void)
{
int ret;
ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_FPGA_CONFIG_COMP, NULL, 0U,
CMD_CASUAL, NULL, NULL);
if (ret != 0) {
INFO("SOCFPGA: FPGA configuration complete response, Return Code: 0x%x\n",
MBOX_RESP_ERR(-ret));
return MBOX_RET_ERROR;
}
return MBOX_RET_OK;
}
int intel_mailbox_get_config_status(uint32_t cmd, bool init_done)
{
int status;

235
plat/intel/soc/common/soc/socfpga_reset_manager.c
View file

@ -404,10 +404,11 @@ int socfpga_bridges_enable(uint32_t mask)
uint32_t brg_lst = 0;
#endif
/**************** SOC2FPGA ****************/
/* Enable s2f bridge */
socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
/**************** SOC2FPGA ****************/
brg_lst = mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST));
if ((brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA)
&& ((brg_lst & RSTMGR_BRGMODRSTMASK_SOC2FPGA) != 0)) {
@ -593,6 +594,8 @@ int socfpga_bridges_enable(uint32_t mask)
}
#endif
/**************** FPGA2SOC ****************/
/* Enable f2s bridge */
socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
&f2s_force_drain, &f2s_en,
@ -603,89 +606,28 @@ int socfpga_bridges_enable(uint32_t mask)
if ((brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC)
&& ((brg_lst & RSTMGR_BRGMODRSTMASK_FPGA2SOC) != 0)) {
/*
* To request handshake
* Write Reset Manager hdsken[fpgahsen] = 1
* To deassert reset
* Write Reset Manager brgmodrst[fpga2soc] = 0
*/
VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
VERBOSE("Deassert F2S ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_FPGA2SOC);
/*
* To request handshake
* Write Reset Manager hdskreq[fpgahsreq] = 1
* To clear handshake fpgahsack
* Write Reset Manager hdskreq[fpgahsack] = 1
*/
VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
/*
* To poll idle status
* Read Reset Manager hdskack[fpgahsack] = 1
*/
VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
300);
}
if (ret < 0) {
ERROR("FPGA bridge fpga handshake fpgahsreq: Timeout\n");
}
/*
* To fence and drain traffic
* Write Reset Manager hdskreq[f2s_flush_req] = 1
*/
VERBOSE("Set F2S hdskreq(f2s_flush_req) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_FPGA2SOCREQ);
/*
* To poll idle status
* Read Reset Manager hdskack[f2s_flush_ack] = 1
*/
VERBOSE("Get F2S hdskack(f2s_flush_ack) ...\n");
if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK,
300);
}
if (ret < 0) {
ERROR("F2S bridge fpga handshake f2sdram_flush_req: Timeout\n");
}
VERBOSE("Clear FPGA hdskack(fpgahsack) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK);
/*
* To clear idle request
* Write Reset Manager hdskreq[fpgahsreq] = 1
* Write Reset Manager hdskreq[fpgahsreq] = 0
*/
VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
/*
* To clear idle request
* Write Reset Manager hdskreq[f2s_flush_req] = 1
*/
VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_FPGA2SOCREQ);
/*
* To poll idle status
* Read Reset Manager hdskack[f2s_flush_ack] = 0
*/
VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
300);
}
if (ret < 0) {
ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
}
RSTMGR_HDSKACK_FPGAHSREQ);
/*
* To poll idle status
@ -695,8 +637,9 @@ int socfpga_bridges_enable(uint32_t mask)
if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
300);
RSTMGR_HDSKACK_FPGAHSACK,
RSTMGR_HDSKACK_FPGAHSACK_DASRT,
1000);
}
if (ret < 0) {
@ -704,27 +647,46 @@ int socfpga_bridges_enable(uint32_t mask)
}
/*
* To assert reset
* Write Reset Manager brgmodrst[fpga2soc] = 1
* To clear handshake f2s_flush_ack
* Write Reset Manager hdskreq[f2s_flush_ack] = 1
*/
VERBOSE("Assert F2S ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
udelay(1000);
VERBOSE("Clear F2S hdskack(f2s_flush_ack) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_F2S_FLUSH);
/*
* To deassert reset
* Write Reset Manager brgmodrst[fpga2soc] = 0
* To clear idle request
* Write Reset Manager hdskreq[f2s_flush_req] = 0
*/
VERBOSE("Deassert F2S ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_F2S_FLUSH);
/* Write System Manager f2s bridge control register[f2soc_enable] = 1 */
/*
* To poll idle status
* Read Reset Manager hdskack[f2s_flush_ack] = 0
*/
VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGA2SOCACK,
RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
1000);
}
if (ret < 0) {
ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
}
/* Write System Manager f2s_bridge_ctrl [f2soc_enable] = 1 */
VERBOSE("Deassert F2S f2soc_enable ...\n");
mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
SYSMGR_F2S_BRIDGE_CTRL_EN);
SYSMGR_F2S_BRIDGE_CTRL_EN);
}
/**************** FPGA2SDRAM ****************/
/* Enable FPGA2SDRAM bridge */
if ((brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0)
&& ((brg_lst & RSTMGR_BRGMODRSTMASK_F2SDRAM0) != 0)) {
@ -932,6 +894,8 @@ int socfpga_bridges_disable(uint32_t mask)
uint32_t f2s_respempty = 0;
uint32_t f2s_cmdidle = 0;
/**************** SOC2FPGA ****************/
/* Disable s2f bridge */
socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
@ -973,6 +937,8 @@ int socfpga_bridges_disable(uint32_t mask)
udelay(1000);
}
/**************** LWSOCFPGA ****************/
/* Disable LWSOC2FPGA bridge */
if (brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) {
/*
@ -1035,6 +1001,8 @@ int socfpga_bridges_disable(uint32_t mask)
}
#endif
/**************** FPGA2SOC ****************/
/* Disable f2s bridge */
socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
&f2s_force_drain, &f2s_en,
@ -1042,69 +1010,92 @@ int socfpga_bridges_disable(uint32_t mask)
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
/* Disable FPGA2SOC bridge */
if (brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC) {
/*
* To request handshake
* Write Reset Manager hdsken[f2soc_flush] = 1
*/
VERBOSE("Enable FPGA hdsken(f2soc_flush) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
RSTMGR_HDSKEN_F2S_FLUSH);
/*
* To request handshake
* Write Reset Manager hdsken[fpgahsen] = 1
*/
VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
VERBOSE("Enable FPGA hdsken(fpgahsen) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
/*
* To clear handshake request
* Write Reset Manager hdskreq[fpgahsreq] = 0
* To clear handshake fpgahsack
* Write Reset Manager hdskack[fpgahsack] = 1
*/
VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
VERBOSE("Clear FPGA hdskack(fpgahsack) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK);
/*
* To clear handshake request
* Write Reset Manager hdskreq[f2s_flush_req] = 0
* To set handshake request
* Write Reset Manager hdskreq[fpgahsreq] = 1
*/
VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_FPGA2SOCREQ);
VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_FPGAHSREQ);
/*
* To poll idle status
* Read Reset Manager hdskack[f2s_flush_ack] = 0
*/
VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
300);
if (ret < 0) {
ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
}
/*
* To poll idle status
* Read Reset Manager hdskack[fpgahsack] = 0
* Read Reset Manager hdskack[fpgahsack] = 1
*/
VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
300);
RSTMGR_HDSKACK_FPGAHSACK,
RSTMGR_HDSKACK_FPGAHSACK,
1000);
if (ret < 0) {
ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n");
}
/*
* To clear handshake f2s_flush_ack
* Write Reset Manager hdskack[f2s_flush_ack] = 1
*/
VERBOSE("Clear F2S hdskack(f2s_flush_ack) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_F2S_FLUSH);
/*
* To set handshake request
* Write Reset Manager hdskreq[f2s_flush_req] = 1
*/
VERBOSE("Set FPGA hdskreq(f2s_flush_req) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_F2S_FLUSH);
/*
* To poll idle status
* Read Reset Manager hdskack[f2s_flush_ack] = 1
*/
VERBOSE("Get FPGA hdskack(f2s_flush_ack) ...\n");
ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGA2SOCACK,
RSTMGR_HDSKACK_F2S_FLUSH,
1000);
if (ret < 0) {
ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
}
/*
* To assert reset
* Write Reset Manager brgmodrst[fpga2soc] = 1
*/
VERBOSE("Assert F2S ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
udelay(1000);
/* Write System Manager f2s bridge control register[f2soc_enable] = 0 */
VERBOSE("Assert F2S f2soc_enable ...\n");
mmio_clrbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
SYSMGR_F2S_BRIDGE_CTRL_EN);
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_FPGA2SOC);
}
/**************** FPGA2SDRAM ****************/
/* Disable FPGA2SDRAM bridge */
if (brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0) {
/*

13
plat/intel/soc/common/socfpga_sip_svc.c
View file

@ -222,6 +222,19 @@ static int intel_fpga_config_start(uint32_t flag)
unsigned int size = 0;
unsigned int resp_len = ARRAY_SIZE(response);
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
/*
* To trigger isolation
* FPGA configuration complete signal should be de-asserted
*/
INFO("SOCFPGA: Request SDM to trigger isolation\n");
status = mailbox_send_fpga_config_comp();
if (status < 0) {
INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n");
}
#endif
request_type = RECONFIGURATION;
if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {