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feat(mt8196): initialize platform for MediaTek MT8196
- Add basic platform setup. - Add MT8196 documentation at docs/plat/. - Add generic CPU helper functions. - Add basic register address. - Add timer driver configuration. Change-Id: I07fcdeb785fcda4a955c11c39a345da4ad05ef04 Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
This commit is contained in:
Gavin Liu
Gavin Liu
parent
3df50a0699
commit
a65fadfbbd
13 changed files with 553 additions and 0 deletions
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@ -24,6 +24,7 @@ Platform Ports
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mt8188
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mt8192
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mt8195
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mt8196
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nvidia-tegra
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warp7
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imx8
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23
docs/plat/mt8196.rst
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23
docs/plat/mt8196.rst
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@ -0,0 +1,23 @@
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MediaTek 8196
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=============
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MediaTek 8196 (MT8196) is a 64-bit ARM SoC introduced by MediaTek in 2024.
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The chip incorporates eight cores - four Cortex-A720 cores, three Cortex-X4
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cores and one Cortex-X925 core.
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Cortex-A720 can operate at up to 2.1 GHz.
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Cortex-X4 can operate at up to 2.8 GHz.
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Cortex-X925 can operate at up to 3.6 GHz.
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Boot Sequence
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-------------
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::
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Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel
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How to Build
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------------
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.. code:: shell
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8196 DEBUG=1 COREBOOT=1
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@ -7,7 +7,12 @@
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#ifndef MT_TIMER_H
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#define MT_TIMER_H
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#include "platform_def.h"
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#ifndef SYSTIMER_BASE
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#define SYSTIMER_BASE (0x10017000)
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#endif
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#define CNTCR_REG (SYSTIMER_BASE + 0x0)
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#define CNTSR_REG (SYSTIMER_BASE + 0x4)
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#define CNTSYS_L_REG (SYSTIMER_BASE + 0x8)
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110
plat/mediatek/helpers/armv9/arch_helpers.S
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110
plat/mediatek/helpers/armv9/arch_helpers.S
Normal file
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@ -0,0 +1,110 @@
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/*
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* Copyright (c) 2024, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_macros.S>
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#include <platform_def.h>
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#if CONFIG_MTK_MCUSYS
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#include <mcucfg.h>
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#endif
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/*
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* Declare as weak function so that can be
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* overwritten by platform helpers
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*/
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.weak platform_mem_init
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.weak plat_core_pos_by_mpidr
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.weak plat_my_core_pos
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.weak plat_mediatek_calc_core_pos
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.global plat_mpidr_by_core_pos
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.global plat_reset_handler
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/* -----------------------------------------------------
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* unsigned long plat_mpidr_by_core_pos(uint32_t cpuid)
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* This function calcuate mpidr by cpu pos if cpu
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* topology is linear.
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*
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* Clobbers: x0-x1
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* -----------------------------------------------------
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*/
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func plat_mpidr_by_core_pos
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lsl x0, x0, #MPIDR_AFF1_SHIFT
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mrs x1, mpidr_el1
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and x1, x1, #MPIDR_MT_MASK
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orr x0, x0, x1
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ret
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endfunc plat_mpidr_by_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_arm_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_mediatek_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* int plat_mediatek_calc_core_pos(u_register_t mpidr);
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*
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* In ARMv8.2, AFF2 is cluster id, AFF1 is core id and
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* AFF0 is thread id. There is only one cluster in ARMv8.2
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* and one thread in current implementation.
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*
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* With this function: CorePos = CoreID (AFF1)
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* we do it with x0 = (x0 >> 8) & 0xff
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* -----------------------------------------------------
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*/
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func plat_mediatek_calc_core_pos
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b plat_core_pos_by_mpidr
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endfunc plat_mediatek_calc_core_pos
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/* ------------------------------------------------------
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* int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
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*
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* This function implements a part of the critical
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* interface between the psci generic layer and the
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* platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index.
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*
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* Clobbers: x0-x1
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* ------------------------------------------------------
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*/
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func plat_core_pos_by_mpidr
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mov x1, #MPIDR_AFFLVL_MASK
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and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
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ret
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endfunc plat_core_pos_by_mpidr
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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* Any memory init, relocation to be done before the
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* platform boots. Called very early in the boot process.
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* --------------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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func plat_reset_handler
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#if CONFIG_MTK_MCUSYS
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mov x10, x30
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bl plat_my_core_pos
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mov x30, x10
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mov w1, #0x1
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lsl w1, w1, w0
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ldr x0, =CPC_MCUSYS_CPU_ON_SW_HINT_SET
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str w1, [x0]
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dsb sy
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#endif
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ret
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endfunc plat_reset_handler
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34
plat/mediatek/include/armv9/arch_def.h
Normal file
34
plat/mediatek/include/armv9/arch_def.h
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@ -0,0 +1,34 @@
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/*
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* Copyright (c) 2024, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARCH_DEF_H
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#define ARCH_DEF_H
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#include <arch.h>
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/* Topology constants */
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#ifndef PLAT_MAX_PWR_LVL
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#endif
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#define PLAT_MAX_RET_STATE MPIDR_AFFLVL1
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#ifndef PLAT_MAX_OFF_STATE
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#define PLAT_MAX_OFF_STATE MPIDR_AFFLVL2
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#endif
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#define PLATFORM_SYSTEM_COUNT 1
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CLUSTER0_CORE_COUNT 8
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 8
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#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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/* Cachline size */
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* ARCH_DEF_H */
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13
plat/mediatek/lib/pm/armv9_0/rules.mk
Normal file
13
plat/mediatek/lib/pm/armv9_0/rules.mk
Normal file
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@ -0,0 +1,13 @@
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#
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# Copyright (c) 2024, MediaTek Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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LOCAL_DIR := $(call GET_LOCAL_DIR)
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MODULE := armv${CONFIG_MTK_PM_ARCH}
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LOCAL_SRCS-y :=
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$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
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38
plat/mediatek/mt8196/include/plat_macros.S
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38
plat/mediatek/mt8196/include/plat_macros.S
Normal file
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2024, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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#include <platform_def.h>
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.section .rodata.gic_reg_name, "aS"
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gicc_regs:
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.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
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" Offset:\t\t\tvalue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t0x"
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.section .rodata.cci_reg_name, "aS"
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cci_iface_regs:
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.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
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/* ---------------------------------------------
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* The below macro prints out relevant GIC
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* registers whenever an unhandled exception
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* is taken in BL31.
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* Clobbers: x0 - x10, x26, x27, sp
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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/* TODO: leave implementation to GIC owner */
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.endm
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#endif /* PLAT_MACROS_S */
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18
plat/mediatek/mt8196/include/plat_private.h
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18
plat/mediatek/mt8196/include/plat_private.h
Normal file
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@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2024, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_PRIVATE_H
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#define PLAT_PRIVATE_H
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/*******************************************************************************
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* Function and variable prototypes
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******************************************************************************/
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void plat_configure_mmu_el3(uintptr_t total_base,
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uintptr_t total_size,
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uintptr_t ro_start,
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uintptr_t ro_limit);
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#endif /* PLAT_PRIVATE_H */
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164
plat/mediatek/mt8196/include/platform_def.h
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164
plat/mediatek/mt8196/include/platform_def.h
Normal file
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@ -0,0 +1,164 @@
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/*
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* Copyright (c) 2024, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <plat/common/common_def.h>
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#include <arch_def.h>
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#define PLAT_PRIMARY_CPU (0x0)
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#define MT_GIC_BASE (0x0C400000)
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#define MCUCFG_BASE (0x0C000000)
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#define MCUCFG_REG_SIZE (0x50000)
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#define IO_PHYS (0x10000000)
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/* Aggregate of all devices for MMU mapping */
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#define MTK_DEV_RNG1_BASE (IO_PHYS)
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#define MTK_DEV_RNG1_SIZE (0x10000000)
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#define TOPCKGEN_BASE (IO_PHYS)
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/*******************************************************************************
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* AUDIO related constants
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******************************************************************************/
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#define AUDIO_BASE (IO_PHYS + 0x0a110000)
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/*******************************************************************************
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* SPM related constants
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******************************************************************************/
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#define SPM_BASE (IO_PHYS + 0x0C004000)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define UART0_BASE (IO_PHYS + 0x06000000)
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#define UART_BAUDRATE (115200)
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/*******************************************************************************
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* Infra IOMMU related constants
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******************************************************************************/
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#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
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#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000)
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#define PERICFG_AO_BASE (IO_PHYS + 0x06630000)
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#define PERICFG_AO_REG_SIZE (0x1000)
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/*******************************************************************************
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* GIC-600 & interrupt handling related constants
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******************************************************************************/
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/* Base MTK_platform compatible GIC memory map */
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#define BASE_GICD_BASE (MT_GIC_BASE)
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#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
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#define MTK_GIC_REG_SIZE 0x400000
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/*******************************************************************************
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* MM IOMMU & SMI related constants
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******************************************************************************/
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#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000)
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#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000)
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#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000)
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#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000)
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#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000)
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#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000)
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#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000)
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#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000)
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#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000)
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#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000)
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#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000)
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#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000)
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#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000)
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#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000)
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#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000)
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#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000)
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#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000)
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#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000)
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#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000)
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#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000)
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#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000)
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#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000)
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#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000)
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#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000)
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#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000)
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#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000)
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#define SMI_LARB_REG_RNG_SIZE (0x1000)
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/*******************************************************************************
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* APMIXEDSYS related constants
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******************************************************************************/
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#define APMIXEDSYS (IO_PHYS + 0x0000C000)
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/*******************************************************************************
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* VPPSYS related constants
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******************************************************************************/
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#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
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#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
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/*******************************************************************************
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* VDOSYS related constants
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******************************************************************************/
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#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000)
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#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
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/*******************************************************************************
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* EMI MPU related constants
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*******************************************************************************/
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#define EMI_MPU_BASE (IO_PHYS + 0x00428000)
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#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000)
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_HZ (13000000)
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#define SYS_COUNTER_FREQ_IN_MHZ (13)
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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#define PLATFORM_STACK_SIZE (0x800)
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#define SOC_CHIP_ID U(0x8196)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define TZRAM_BASE (0x94600000)
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#define TZRAM_SIZE (0x00200000)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
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* little space for growth.
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*/
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#define BL31_BASE (TZRAM_BASE + 0x1000)
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
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#define MAX_XLAT_TABLES (128)
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#define MAX_MMAP_REGIONS (512)
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/*******************************************************************************
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* CPU PM definitions
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*******************************************************************************/
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#define PLAT_CPU_PM_B_BUCK_ISO_ID (6)
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#define PLAT_CPU_PM_ILDO_ID (6)
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#define CPU_IDLE_SRAM_BASE (0x11B000)
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#define CPU_IDLE_SRAM_SIZE (0x1000)
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/*******************************************************************************
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* SYSTIMER related definitions
|
||||
******************************************************************************/
|
||||
#define SYSTIMER_BASE (0x1C400000)
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
46
plat/mediatek/mt8196/plat_config.mk
Normal file
46
plat/mediatek/mt8196/plat_config.mk
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
#
|
||||
# Copyright (c) 2024, MediaTek Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Separate text code and read only data
|
||||
SEPARATE_CODE_AND_RODATA := 1
|
||||
|
||||
# ARMv8.2 and above need enable HW assist coherence
|
||||
HW_ASSISTED_COHERENCY := 1
|
||||
|
||||
# No need coherency memory because of HW assistency
|
||||
USE_COHERENT_MEM := 0
|
||||
|
||||
# GIC600
|
||||
GICV3_SUPPORT_GIC600 := 1
|
||||
|
||||
#
|
||||
# MTK options
|
||||
#
|
||||
PLAT_EXTRA_RODATA_INCLUDES := 1
|
||||
USE_PMIC_WRAP_INIT_V2 := 1
|
||||
|
||||
# Configs for A78 and A55
|
||||
CTX_INCLUDE_AARCH32_REGS := 0
|
||||
|
||||
CONFIG_ARCH_ARM_V9 := y
|
||||
CONFIG_MTK_MCUSYS := y
|
||||
MCUSYS_VERSION := v1
|
||||
CONFIG_MTK_PM_SUPPORT := y
|
||||
CONFIG_MTK_PM_ARCH := 9_0
|
||||
CONFIG_MTK_CPU_PM_SUPPORT := y
|
||||
CONFIG_MTK_CPU_PM_ARCH := 5_4
|
||||
CONFIG_MTK_SMP_EN := n
|
||||
CONFIG_MTK_CPU_SUSPEND_EN := y
|
||||
CONFIG_MTK_SPM_VERSION := mt8196
|
||||
CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND := y
|
||||
CPU_PM_TINYSYS_SUPPORT := y
|
||||
MTK_PUBEVENT_ENABLE := y
|
||||
|
||||
ENABLE_FEAT_AMU := 1
|
||||
ENABLE_FEAT_ECV := 1
|
||||
ENABLE_FEAT_FGT := 1
|
||||
ENABLE_FEAT_HCX := 1
|
||||
ENABLE_SVE_FOR_SWD := 1
|
||||
22
plat/mediatek/mt8196/plat_mmap.c
Normal file
22
plat/mediatek/mt8196/plat_mmap.c
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2024, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <mtk_mmap_pool.h>
|
||||
|
||||
static const mmap_region_t plat_mmap[] = {
|
||||
MAP_REGION_FLAT(MT_GIC_BASE, MTK_GIC_REG_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(CPU_IDLE_SRAM_BASE, CPU_IDLE_SRAM_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
{ 0 }
|
||||
};
|
||||
DECLARE_MTK_MMAP_REGIONS(plat_mmap);
|
||||
51
plat/mediatek/mt8196/platform.mk
Normal file
51
plat/mediatek/mt8196/platform.mk
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
#
|
||||
# Copyright (c) 2024, MediaTek Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
MTK_PLAT := plat/mediatek
|
||||
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
|
||||
MTK_SOC := ${PLAT}
|
||||
ARM_ARCH_MAJOR := 9
|
||||
|
||||
include plat/mediatek/build_helpers/mtk_build_helpers.mk
|
||||
include drivers/arm/gic/v3/gicv3.mk
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
||||
PLAT_INCLUDES := -I${MTK_PLAT}/common \
|
||||
-I${MTK_PLAT}/include \
|
||||
-I${MTK_PLAT}/include/${ARCH_VERSION} \
|
||||
-I${MTK_PLAT} \
|
||||
-I${MTK_PLAT_SOC}/include \
|
||||
-Idrivers/arm/gic \
|
||||
|
||||
MODULES-y += $(MTK_PLAT)/common
|
||||
MODULES-y += $(MTK_PLAT)/lib/mtk_init
|
||||
MODULES-y += $(MTK_PLAT)/lib/pm
|
||||
MODULES-y += $(MTK_PLAT)/drivers/mcusys
|
||||
MODULES-y += $(MTK_PLAT)/drivers/timer
|
||||
MODULES-y += $(MTK_PLAT)/helpers
|
||||
MODULES-y += $(MTK_PLAT)/topology
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
|
||||
drivers/ti/uart/aarch64/16550_console.S \
|
||||
lib/bl_aux_params/bl_aux_params.c
|
||||
|
||||
BL31_SOURCES += drivers/delay_timer/delay_timer.c \
|
||||
drivers/delay_timer/generic_delay_timer.c \
|
||||
lib/cpus/aarch64/cortex_a720.S \
|
||||
lib/cpus/aarch64/cortex_x4.S \
|
||||
lib/cpus/aarch64/cortex_x925.S \
|
||||
${GICV3_SOURCES} \
|
||||
${XLAT_TABLES_LIB_SRCS} \
|
||||
plat/common/plat_gicv3.c \
|
||||
plat/common/plat_psci_common.c \
|
||||
plat/common/aarch64/crash_console_helpers.S \
|
||||
${MTK_PLAT}/common/mtk_plat_common.c \
|
||||
${MTK_PLAT}/common/params_setup.c \
|
||||
$(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c
|
||||
|
||||
include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk
|
||||
|
||||
include lib/coreboot/coreboot.mk
|
||||
28
plat/mediatek/topology/armv9/topology.c
Normal file
28
plat/mediatek/topology/armv9/topology.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) 2024, Mediatek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <lib/psci/psci.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#pragma weak plat_get_power_domain_tree_desc
|
||||
|
||||
static const unsigned char mtk_power_domain_tree_desc[] = {
|
||||
/* Number of root nodes */
|
||||
PLATFORM_SYSTEM_COUNT,
|
||||
/* Number of children for the root node */
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
/* Number of children for the first cluster node */
|
||||
PLATFORM_CLUSTER0_CORE_COUNT
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the default topology tree information.
|
||||
******************************************************************************/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return mtk_power_domain_tree_desc;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue