From a65fadfbbd5919939bfe367fe3f2d3c22ca4cbf0 Mon Sep 17 00:00:00 2001 From: Gavin Liu Date: Mon, 21 Oct 2024 14:22:19 +0800 Subject: [PATCH] feat(mt8196): initialize platform for MediaTek MT8196 - Add basic platform setup. - Add MT8196 documentation at docs/plat/. - Add generic CPU helper functions. - Add basic register address. - Add timer driver configuration. Change-Id: I07fcdeb785fcda4a955c11c39a345da4ad05ef04 Signed-off-by: Gavin Liu --- docs/plat/index.rst | 1 + docs/plat/mt8196.rst | 23 +++ plat/mediatek/drivers/timer/mt_timer.h | 5 + plat/mediatek/helpers/armv9/arch_helpers.S | 110 +++++++++++++ plat/mediatek/include/armv9/arch_def.h | 34 ++++ plat/mediatek/lib/pm/armv9_0/rules.mk | 13 ++ plat/mediatek/mt8196/include/plat_macros.S | 38 +++++ plat/mediatek/mt8196/include/plat_private.h | 18 +++ plat/mediatek/mt8196/include/platform_def.h | 164 ++++++++++++++++++++ plat/mediatek/mt8196/plat_config.mk | 46 ++++++ plat/mediatek/mt8196/plat_mmap.c | 22 +++ plat/mediatek/mt8196/platform.mk | 51 ++++++ plat/mediatek/topology/armv9/topology.c | 28 ++++ 13 files changed, 553 insertions(+) create mode 100644 docs/plat/mt8196.rst create mode 100644 plat/mediatek/helpers/armv9/arch_helpers.S create mode 100644 plat/mediatek/include/armv9/arch_def.h create mode 100644 plat/mediatek/lib/pm/armv9_0/rules.mk create mode 100644 plat/mediatek/mt8196/include/plat_macros.S create mode 100644 plat/mediatek/mt8196/include/plat_private.h create mode 100644 plat/mediatek/mt8196/include/platform_def.h create mode 100644 plat/mediatek/mt8196/plat_config.mk create mode 100644 plat/mediatek/mt8196/plat_mmap.c create mode 100644 plat/mediatek/mt8196/platform.mk create mode 100644 plat/mediatek/topology/armv9/topology.c diff --git a/docs/plat/index.rst b/docs/plat/index.rst index a8e0c8dc9..0b53d1dcd 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -24,6 +24,7 @@ Platform Ports mt8188 mt8192 mt8195 + mt8196 nvidia-tegra warp7 imx8 diff --git a/docs/plat/mt8196.rst b/docs/plat/mt8196.rst new file mode 100644 index 000000000..e4b6c63ee --- /dev/null +++ b/docs/plat/mt8196.rst @@ -0,0 +1,23 @@ +MediaTek 8196 +============= + +MediaTek 8196 (MT8196) is a 64-bit ARM SoC introduced by MediaTek in 2024. +The chip incorporates eight cores - four Cortex-A720 cores, three Cortex-X4 +cores and one Cortex-X925 core. +Cortex-A720 can operate at up to 2.1 GHz. +Cortex-X4 can operate at up to 2.8 GHz. +Cortex-X925 can operate at up to 3.6 GHz. + +Boot Sequence +------------- + +:: + + Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel + +How to Build +------------ + +.. code:: shell + + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8196 DEBUG=1 COREBOOT=1 diff --git a/plat/mediatek/drivers/timer/mt_timer.h b/plat/mediatek/drivers/timer/mt_timer.h index 1c08f9099..fafbbcfe6 100644 --- a/plat/mediatek/drivers/timer/mt_timer.h +++ b/plat/mediatek/drivers/timer/mt_timer.h @@ -7,7 +7,12 @@ #ifndef MT_TIMER_H #define MT_TIMER_H +#include "platform_def.h" + +#ifndef SYSTIMER_BASE #define SYSTIMER_BASE (0x10017000) +#endif + #define CNTCR_REG (SYSTIMER_BASE + 0x0) #define CNTSR_REG (SYSTIMER_BASE + 0x4) #define CNTSYS_L_REG (SYSTIMER_BASE + 0x8) diff --git a/plat/mediatek/helpers/armv9/arch_helpers.S b/plat/mediatek/helpers/armv9/arch_helpers.S new file mode 100644 index 000000000..f96fff942 --- /dev/null +++ b/plat/mediatek/helpers/armv9/arch_helpers.S @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2024, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#if CONFIG_MTK_MCUSYS +#include +#endif + + /* + * Declare as weak function so that can be + * overwritten by platform helpers + */ + .weak platform_mem_init + .weak plat_core_pos_by_mpidr + .weak plat_my_core_pos + .weak plat_mediatek_calc_core_pos + .global plat_mpidr_by_core_pos + .global plat_reset_handler + + /* ----------------------------------------------------- + * unsigned long plat_mpidr_by_core_pos(uint32_t cpuid) + * This function calcuate mpidr by cpu pos if cpu + * topology is linear. + * + * Clobbers: x0-x1 + * ----------------------------------------------------- + */ +func plat_mpidr_by_core_pos + lsl x0, x0, #MPIDR_AFF1_SHIFT + mrs x1, mpidr_el1 + and x1, x1, #MPIDR_MT_MASK + orr x0, x0, x1 + ret +endfunc plat_mpidr_by_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_arm_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_mediatek_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * int plat_mediatek_calc_core_pos(u_register_t mpidr); + * + * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and + * AFF0 is thread id. There is only one cluster in ARMv8.2 + * and one thread in current implementation. + * + * With this function: CorePos = CoreID (AFF1) + * we do it with x0 = (x0 >> 8) & 0xff + * ----------------------------------------------------- + */ +func plat_mediatek_calc_core_pos + b plat_core_pos_by_mpidr +endfunc plat_mediatek_calc_core_pos + + /* ------------------------------------------------------ + * int32_t plat_core_pos_by_mpidr(u_register_t mpidr) + * + * This function implements a part of the critical + * interface between the psci generic layer and the + * platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. + * + * Clobbers: x0-x1 + * ------------------------------------------------------ + */ +func plat_core_pos_by_mpidr + mov x1, #MPIDR_AFFLVL_MASK + and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT + ret +endfunc plat_core_pos_by_mpidr + + /* -------------------------------------------------------- + * void platform_mem_init (void); + * + * Any memory init, relocation to be done before the + * platform boots. Called very early in the boot process. + * -------------------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + +func plat_reset_handler +#if CONFIG_MTK_MCUSYS + mov x10, x30 + bl plat_my_core_pos + mov x30, x10 + mov w1, #0x1 + lsl w1, w1, w0 + ldr x0, =CPC_MCUSYS_CPU_ON_SW_HINT_SET + str w1, [x0] + dsb sy +#endif + + ret +endfunc plat_reset_handler diff --git a/plat/mediatek/include/armv9/arch_def.h b/plat/mediatek/include/armv9/arch_def.h new file mode 100644 index 000000000..d1d5a1429 --- /dev/null +++ b/plat/mediatek/include/armv9/arch_def.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ARCH_DEF_H +#define ARCH_DEF_H + +#include + +/* Topology constants */ +#ifndef PLAT_MAX_PWR_LVL +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 +#endif +#define PLAT_MAX_RET_STATE MPIDR_AFFLVL1 + +#ifndef PLAT_MAX_OFF_STATE +#define PLAT_MAX_OFF_STATE MPIDR_AFFLVL2 +#endif + +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_CLUSTER0_CORE_COUNT 8 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 8 +#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +/* Cachline size */ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) +#endif /* ARCH_DEF_H */ diff --git a/plat/mediatek/lib/pm/armv9_0/rules.mk b/plat/mediatek/lib/pm/armv9_0/rules.mk new file mode 100644 index 000000000..08a795722 --- /dev/null +++ b/plat/mediatek/lib/pm/armv9_0/rules.mk @@ -0,0 +1,13 @@ +# +# Copyright (c) 2024, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := armv${CONFIG_MTK_PM_ARCH} + +LOCAL_SRCS-y := + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/mt8196/include/plat_macros.S b/plat/mediatek/mt8196/include/plat_macros.S new file mode 100644 index 000000000..c646edd22 --- /dev/null +++ b/plat/mediatek/mt8196/include/plat_macros.S @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception + * is taken in BL31. + * Clobbers: x0 - x10, x26, x27, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + /* TODO: leave implementation to GIC owner */ + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/mediatek/mt8196/include/plat_private.h b/plat/mediatek/mt8196/include/plat_private.h new file mode 100644 index 000000000..1ed1973c5 --- /dev/null +++ b/plat/mediatek/mt8196/include/plat_private.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_configure_mmu_el3(uintptr_t total_base, + uintptr_t total_size, + uintptr_t ro_start, + uintptr_t ro_limit); + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/mediatek/mt8196/include/platform_def.h b/plat/mediatek/mt8196/include/platform_def.h new file mode 100644 index 000000000..66c7cf855 --- /dev/null +++ b/plat/mediatek/mt8196/include/platform_def.h @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2024, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include + +#include + +#define PLAT_PRIMARY_CPU (0x0) + +#define MT_GIC_BASE (0x0C400000) +#define MCUCFG_BASE (0x0C000000) +#define MCUCFG_REG_SIZE (0x50000) +#define IO_PHYS (0x10000000) + +/* Aggregate of all devices for MMU mapping */ +#define MTK_DEV_RNG1_BASE (IO_PHYS) +#define MTK_DEV_RNG1_SIZE (0x10000000) + +#define TOPCKGEN_BASE (IO_PHYS) + +/******************************************************************************* + * AUDIO related constants + ******************************************************************************/ +#define AUDIO_BASE (IO_PHYS + 0x0a110000) + +/******************************************************************************* + * SPM related constants + ******************************************************************************/ +#define SPM_BASE (IO_PHYS + 0x0C004000) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define UART0_BASE (IO_PHYS + 0x06000000) +#define UART_BAUDRATE (115200) + +/******************************************************************************* + * Infra IOMMU related constants + ******************************************************************************/ +#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) +#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000) +#define PERICFG_AO_BASE (IO_PHYS + 0x06630000) +#define PERICFG_AO_REG_SIZE (0x1000) + +/******************************************************************************* + * GIC-600 & interrupt handling related constants + ******************************************************************************/ +/* Base MTK_platform compatible GIC memory map */ +#define BASE_GICD_BASE (MT_GIC_BASE) +#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) +#define MTK_GIC_REG_SIZE 0x400000 + +/******************************************************************************* + * MM IOMMU & SMI related constants + ******************************************************************************/ +#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) +#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) +#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) +#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) +#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) +#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) +#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) +#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) +#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) +#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) +#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) +#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) +#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) +#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) +#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) +#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) +#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) +#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) +#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) +#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) +#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) +#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) +#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) +#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) +#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) +#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) +#define SMI_LARB_REG_RNG_SIZE (0x1000) + +/******************************************************************************* + * APMIXEDSYS related constants + ******************************************************************************/ +#define APMIXEDSYS (IO_PHYS + 0x0000C000) + +/******************************************************************************* + * VPPSYS related constants + ******************************************************************************/ +#define VPPSYS0_BASE (IO_PHYS + 0x04000000) +#define VPPSYS1_BASE (IO_PHYS + 0x04f00000) + +/******************************************************************************* + * VDOSYS related constants + ******************************************************************************/ +#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) +#define VDOSYS1_BASE (IO_PHYS + 0x0C100000) + +/******************************************************************************* + * EMI MPU related constants + *******************************************************************************/ +#define EMI_MPU_BASE (IO_PHYS + 0x00428000) +#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000) + +/******************************************************************************* + * System counter frequency related constants + ******************************************************************************/ +#define SYS_COUNTER_FREQ_IN_HZ (13000000) +#define SYS_COUNTER_FREQ_IN_MHZ (13) + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ +#define PLATFORM_STACK_SIZE (0x800) +#define SOC_CHIP_ID U(0x8196) + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define TZRAM_BASE (0x94600000) +#define TZRAM_SIZE (0x00200000) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL3-1 debug size plus a + * little space for growth. + */ +#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) +#define MAX_XLAT_TABLES (128) +#define MAX_MMAP_REGIONS (512) + +/******************************************************************************* + * CPU PM definitions + *******************************************************************************/ +#define PLAT_CPU_PM_B_BUCK_ISO_ID (6) +#define PLAT_CPU_PM_ILDO_ID (6) +#define CPU_IDLE_SRAM_BASE (0x11B000) +#define CPU_IDLE_SRAM_SIZE (0x1000) + +/******************************************************************************* + * SYSTIMER related definitions + ******************************************************************************/ +#define SYSTIMER_BASE (0x1C400000) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk new file mode 100644 index 000000000..dd83b9ab4 --- /dev/null +++ b/plat/mediatek/mt8196/plat_config.mk @@ -0,0 +1,46 @@ +# +# Copyright (c) 2024, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Separate text code and read only data +SEPARATE_CODE_AND_RODATA := 1 + +# ARMv8.2 and above need enable HW assist coherence +HW_ASSISTED_COHERENCY := 1 + +# No need coherency memory because of HW assistency +USE_COHERENT_MEM := 0 + +# GIC600 +GICV3_SUPPORT_GIC600 := 1 + +# +# MTK options +# +PLAT_EXTRA_RODATA_INCLUDES := 1 +USE_PMIC_WRAP_INIT_V2 := 1 + +# Configs for A78 and A55 +CTX_INCLUDE_AARCH32_REGS := 0 + +CONFIG_ARCH_ARM_V9 := y +CONFIG_MTK_MCUSYS := y +MCUSYS_VERSION := v1 +CONFIG_MTK_PM_SUPPORT := y +CONFIG_MTK_PM_ARCH := 9_0 +CONFIG_MTK_CPU_PM_SUPPORT := y +CONFIG_MTK_CPU_PM_ARCH := 5_4 +CONFIG_MTK_SMP_EN := n +CONFIG_MTK_CPU_SUSPEND_EN := y +CONFIG_MTK_SPM_VERSION := mt8196 +CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND := y +CPU_PM_TINYSYS_SUPPORT := y +MTK_PUBEVENT_ENABLE := y + +ENABLE_FEAT_AMU := 1 +ENABLE_FEAT_ECV := 1 +ENABLE_FEAT_FGT := 1 +ENABLE_FEAT_HCX := 1 +ENABLE_SVE_FOR_SWD := 1 diff --git a/plat/mediatek/mt8196/plat_mmap.c b/plat/mediatek/mt8196/plat_mmap.c new file mode 100644 index 000000000..f7f819a68 --- /dev/null +++ b/plat/mediatek/mt8196/plat_mmap.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +static const mmap_region_t plat_mmap[] = { + MAP_REGION_FLAT(MT_GIC_BASE, MTK_GIC_REG_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(CPU_IDLE_SRAM_BASE, CPU_IDLE_SRAM_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; +DECLARE_MTK_MMAP_REGIONS(plat_mmap); diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk new file mode 100644 index 000000000..cd428b2ce --- /dev/null +++ b/plat/mediatek/mt8196/platform.mk @@ -0,0 +1,51 @@ +# +# Copyright (c) 2024, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +MTK_PLAT := plat/mediatek +MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} +MTK_SOC := ${PLAT} +ARM_ARCH_MAJOR := 9 + +include plat/mediatek/build_helpers/mtk_build_helpers.mk +include drivers/arm/gic/v3/gicv3.mk +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_INCLUDES := -I${MTK_PLAT}/common \ + -I${MTK_PLAT}/include \ + -I${MTK_PLAT}/include/${ARCH_VERSION} \ + -I${MTK_PLAT} \ + -I${MTK_PLAT_SOC}/include \ + -Idrivers/arm/gic \ + +MODULES-y += $(MTK_PLAT)/common +MODULES-y += $(MTK_PLAT)/lib/mtk_init +MODULES-y += $(MTK_PLAT)/lib/pm +MODULES-y += $(MTK_PLAT)/drivers/mcusys +MODULES-y += $(MTK_PLAT)/drivers/timer +MODULES-y += $(MTK_PLAT)/helpers +MODULES-y += $(MTK_PLAT)/topology + +PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \ + drivers/ti/uart/aarch64/16550_console.S \ + lib/bl_aux_params/bl_aux_params.c + +BL31_SOURCES += drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + lib/cpus/aarch64/cortex_a720.S \ + lib/cpus/aarch64/cortex_x4.S \ + lib/cpus/aarch64/cortex_x925.S \ + ${GICV3_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} \ + plat/common/plat_gicv3.c \ + plat/common/plat_psci_common.c \ + plat/common/aarch64/crash_console_helpers.S \ + ${MTK_PLAT}/common/mtk_plat_common.c \ + ${MTK_PLAT}/common/params_setup.c \ + $(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c + +include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk + +include lib/coreboot/coreboot.mk diff --git a/plat/mediatek/topology/armv9/topology.c b/plat/mediatek/topology/armv9/topology.c new file mode 100644 index 000000000..d6ecc8392 --- /dev/null +++ b/plat/mediatek/topology/armv9/topology.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#pragma weak plat_get_power_domain_tree_desc + +static const unsigned char mtk_power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_SYSTEM_COUNT, + /* Number of children for the root node */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first cluster node */ + PLATFORM_CLUSTER0_CORE_COUNT +}; + +/******************************************************************************* + * This function returns the default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return mtk_power_domain_tree_desc; +}