feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE

When RME is enabled the RMM is placed at the bottom of the NS RAM,
meaning that NS_DRAM0_BASE has to be located after that.

This patch disscociates the base of the NS RAM as defined by QEMU by
introducing a new define, PLAT_QEMU_DRAM0_BASE.  An offset can be added
to that new define when the software's view of the base memory need to
differ from QEMU.

No change in functionality.

Change-Id: I887f9993d5a61896352cfff17e0d92e2c2b9030a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

plat/qemu/qemu_sbsa/include/platform_def.h

@@ -66,6 +66,9 @@
  */
 #define PLAT_MAX_MEM_NODES	128
 
+/* Where QEMU starts the NS RAM */
+#define PLAT_QEMU_DRAM0_BASE	0x10000000000ULL
+
 /*
  * Partition memory into secure ROM, non-secure DRAM, secure "SRAM",
  * and secure DRAM.
@@ -73,7 +76,12 @@
 #define SEC_ROM_BASE			0x00000000
 #define SEC_ROM_SIZE			0x00020000
 
-#define NS_DRAM0_BASE			0x10000000000ULL
+/*
+ * When the RME extension is enabled, the base of the NS RAM is shifted after
+ * RMM.
+ */
+#define NS_DRAM0_BASE			(PLAT_QEMU_DRAM0_BASE + \
+					NS_DRAM0_BASE_OFFSET)
 #define NS_DRAM0_SIZE			0x00020000000
 
 #define SEC_SRAM_BASE			0x20000000
@@ -377,4 +385,6 @@
 #define QEMU_PRI_BITS		2
 #define PLAT_SP_PRI		0x20
 
+#define NS_DRAM0_BASE_OFFSET	0
+
 #endif /* PLATFORM_DEF_H */

plat/qemu/qemu_sbsa/platform.mk

@@ -60,5 +60,5 @@ ARM_LINUX_KERNEL_AS_BL33	:=	0
 $(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
 $(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
 
-ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
+ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DRAM0_BASE
 $(eval $(call add_define,ARM_PRELOADED_DTB_BASE))