In all non-trivial cases the CPU specific errata functions
already call generic_errata_report, this cuts out the middleman
by directly calling generic_errata_report from
print_errata_status.
The CPU specific errata functions (cpu_ops->errata_func)
can now be removed from all cores, and this field can be
removed from cpu_ops.
Also removes the now unused old errata reporting
function and macros.
Change-Id: Ie4a4fd60429aca37cf434e79c0ce2992a5ff5d68
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.
Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
* changes:
build(deps): bump braces
build(deps): bump the pip group across 1 directory with 2 updates
build(deps): bump the pip group across 1 directory with 7 updates
A macro 'sysreg_bitfield_insert_from_gpr' is introduced for inserting
bitfield from a general register.
Change-Id: I7288a13d70d98e23dc7a93287b04b493ffce9171
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Add DT binding for Arm DSU PMU node.
Change-Id: Iadfb5d3bb3f69c7a771516180d1c165e60eef51d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set for all cores, so set these bits in platform reset handler.
Change-Id: I1db6915939727f0909c05c8b103e37984aadb443
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
The comment for plat_reset_handler doesn't make sense. It is likely a
copy-and-paste error while adding the code, so remove it.
Change-Id: Iab8c8c799c184fa99966770d47ecb11bbc640515
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
The system register actlr_el2 can be set during CPU or platform reset
handler. E.g. on Arm Total Compute platform, the CLUSTERPMUEN bit of
actlr_el2 is set in the platform reset handler to enable the write
access to DSU PMU registers from EL1. However, as EL2 context gets
restored without saving it beforehand during jump to SPM and next NS
image, therefore, the initialized value of actlr_el2 is not retained.
To fix this issue, keep track of actlr_el2 value during the EL2 context
initialization. This applies for both secure and non-secure security
state.
Change-Id: I1bd7b984216c042c056ad20c6724bedce5a6a3e2
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Include platform.h file in order to remove following compiler errors,
as some warnings are being treated as errors now.
error: implicit declaration of function
'plat_core_pos_by_mpidr'[-Wimplicit-function-declaration]
Change-Id: Ie223e11e138ec9b0eef7342f450b90b215a49b15
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was changed from 0x40_b10b
(3 bytes) to 4a0f_b10b (4 bytes).
As updating of TL's signature, register value of x1/r1 should be:
In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b -> masked range value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).
Therefore, it requires to separate mask and shift value for register
convention version field when sets each r1/x1.
This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.
2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.
This change is breaking change. It requires some patch for other
softwares (u-boot[4], optee[5]).
Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: 5aa7aa1d3a [3]
Link: https://lists.denx.de/pipermail/u-boot/2024-July/558628.html [4]
Link: https://github.com/OP-TEE/optee_os/pull/6933 [5]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ie417e054a7a4c192024a2679419e99efeded1705
In a system enabled with RME, the function
'xlat_get_mem_attributes_internal' fails to accurately provide
'output PA space' for Realm and Root memory because it does not
consider the 'nse' bit in page table descriptor.
This patch resolves the issue by extracting the 'nse' bit value.
As a result, it ensures correct retrieval of attributes
in RME-enabled systems while maintaining unaffected attribute
retrieval for non-RME systems.
Change-Id: If2d01545b921c9074f48c52a98027ff331e14237
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* changes:
feat(fvp): add SPM manifest for OP-TEE at S-EL1 without S-EL2/Hafnium
fix(fvp): update the memory size allocated to optee at EL1
fix(fvp): add DRAM memory regions that linux kernel can share
feat(fvp): update FF-A version to v1.1 supported by optee
feat(fvp): replace managed-exit with ns-interrupts-action
fix(fvp): add optee specific mem-size attribute
fix(fvp): fix the FF-A optee manifest by adding the boot info node
modify the print logs when an erratum workaround does not
need to be applied to a certain revision/variant of the CPU.
Change-Id: I8f60636320f617ecd4ed88ee1fbf7a3e3e4517ee
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
When SPD is set to none, it means we don't run any secure OS on the
system. We should make this memory region available to kernel.
Change-Id: Ia83ff4a7d25de38a5d845b7ee1367bafed43bbdd
Signed-off-by: Yidi Lin <yidilin@chromium.org>
This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6d2b614affb9067b2bc3d7bf0ae7d169d031592a
This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a
* changes:
feat(nxp-clk): set rate for clock fixed divider
feat(nxp-clk): add A53 clock objects
feat(nxp-clk): set rate for PLL divider objects
feat(nxp-clk): set rate for PLL objects
MT8195 features four Cortex-A78 cores not Cortex-A76.
Change-Id: I62c60373e7a3e570bcadaeaf065ca0f7473cb838
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.
Change-Id: I8a29a2c5b1a829db0c396407c3517c9e66caaa93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
These objects are needed to allow early enablement of the A53 core
clock.
Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add implementation for ARM PLL divider rate set mechanism.
Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add implementation for ARM PLL rate set mechanism.
Change-Id: Ic859567bd67747f173d425158cdc581801f7446c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Provide manifest to boot OP-TEE at S-EL1 running SPMC with secure EL2
disabled and TF-A at secure EL3 running SPMD.
Change-Id: If8547b5a514fb48eec88a8d56d718f1c1591cf1f
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Update the memory size allocated to optee at EL1 to 0xd80000 to match
the size specified by mem-size in optee manifest.
Change-Id: I6826a56d0f68a6a2b5181f849a741a9bf1f0829b
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The memory regions that Linux kernel can share including TX/RX buffers
encompass the entire DRAM. Update it accordingly. Without this,
when the Linux kernel call FFA_RXTX_MAP, it fails sometime and the
below error from the secure world appears:
| ERROR: arch_other_world_vm_configure_rxtx_map: send page is invalid
| (expected 0x87, got 0x7c)
Change-Id: Idb40907af2e0c1d4e60979b4948db2fc70971145
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
OPTEE now supports FF-A v1.1, lets us bump the FF-A version in the
OPTEE FF-A manifest.
Change-Id: Ia51cbe1af619895945240004a4163a4c4bda2ee5
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Without the mem-size attribute, the OPTEE boot panics with below
error:
| get_sec_mem_from_manifest:1594 Can't read "mem-size" from FF-A
| manifest at 0x6281000: error -1
| Panic at core/arch/arm/kernel/boot.c:1596 <get_sec_mem_from_manifest>
| TEE load address @ 0x6284000
| Call stack:
| 0x0628c7fc
| 0x06298788
| 0x0628c480
Adding the mem-size attribute fixes the boot. This is OPTEE specific
extension.
Change-Id: I2801c8b4a89cffafff14c788319ad106b03ffef0
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Without the FF-A manifest boot info node, the OPTEE boot as S-EL1 VM
crashes currently with the below error:
| WARNING: Stage-2 page fault: pc=0x628c41c, vmid=0x8001, vcpu=0,
| vaddr=0xd00000, ipaddr=0xd00000, mode=0x1 0x7c
| NOTICE: Injecting Data Abort exception into VM 0x8001.
Adding the boot info node fixes the OPTEE boot.
While at it, also update copyright year in the file.
Change-Id: I1fd0bf4e38bb95deedc74fa04d1e6bb057424c04
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
