mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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feat(rk3576): support rk3576
rk3576 is an Octa-core soc with Cortex-a53/a72 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I67a019822bd4af13e4a3cdd09cf06202f4922cc4 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
This commit is contained in:
XiaoDong Huang
parent
02f0e6e4f9
commit
036935a814
26 changed files with 7242 additions and 3 deletions
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@ -11,6 +11,7 @@ This includes right now:
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- rk3368: Octa-Core Cortex-A53
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- rk3399: Hexa-Core Cortex-A53/A72
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- rk3566/rk3568: Quad-Core Cortex-A55
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- rk3576: Octa-Core Cortex-A53/A72
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- rk3588: Octa-Core Cortex-A55/A76
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@ -1,9 +1,10 @@
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/*
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* Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2025, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <platform_def.h>
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@ -58,7 +59,18 @@ DEFINE_CONFIGURE_MMU_EL(3)
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unsigned int plat_get_syscnt_freq2(void)
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{
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#ifdef SYS_COUNTER_FREQ_IN_TICKS
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return SYS_COUNTER_FREQ_IN_TICKS;
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#else
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static int sys_counter_freq_in_hz;
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if (sys_counter_freq_in_hz == 0)
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sys_counter_freq_in_hz = read_cntfrq_el0();
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assert(sys_counter_freq_in_hz != 0);
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return sys_counter_freq_in_hz;
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#endif
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}
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void plat_cci_init(void)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2025, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -28,6 +28,9 @@ extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
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extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
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extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end;
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extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end;
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extern uint32_t __bl31_pmusram_text_start, __bl31_pmusram_text_end;
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extern uint32_t __bl31_pmusram_data_start, __bl31_pmusram_data_end;
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extern uint32_t __bl31_pmusram_text_real_end, __bl31_pmusram_data_real_end;
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extern uint32_t __sram_incbin_start, __sram_incbin_end;
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extern uint32_t __sram_incbin_real_end;
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143
plat/rockchip/common/scmi/rockchip_common_clock.c
Normal file
143
plat/rockchip/common/scmi/rockchip_common_clock.c
Normal file
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@ -0,0 +1,143 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
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*/
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#include <assert.h>
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#include <errno.h>
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#include <drivers/scmi.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <plat_private.h>
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#include <scmi_clock.h>
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#define MUX_ADDR_INFO 0
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#define MUX_SHIFT_INFO 1
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#define MUX_WIDTH_INFO 2
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#define DIV_ADDR_INFO 3
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#define DIV_SHIFT_INFO 4
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#define DIV_WIDTH_INFO 5
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#define GATE_ADDR_INFO 6
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#define GATE_SHIFT_INFO 7
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#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
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#define abs(x) ({ \
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long ret; \
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if (sizeof(x) == sizeof(long)) { \
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long __x = (x); \
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ret = (__x < 0) ? -__x : __x; \
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} else { \
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int __x = (x); \
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ret = (__x < 0) ? -__x : __x; \
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} \
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ret; \
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})
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static unsigned long clk_scmi_common_get_parent_rate(rk_scmi_clock_t *clock,
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int id)
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{
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rk_scmi_clock_t *p_clock;
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if (clock->is_dynamic_prate != 0) {
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p_clock = rockchip_scmi_get_clock(0, clock->parent_table[id]);
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if (p_clock == NULL)
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return 0;
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if ((p_clock->clk_ops != NULL) && (p_clock->clk_ops->get_rate != NULL))
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return p_clock->clk_ops->get_rate(p_clock);
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else
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return 0;
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} else {
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return clock->parent_table[id];
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}
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}
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unsigned long clk_scmi_common_get_rate(rk_scmi_clock_t *clock)
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{
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unsigned long parent_rate, sel, div;
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sel = mmio_read_32(clock->info[MUX_ADDR_INFO]) >>
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clock->info[MUX_SHIFT_INFO];
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sel = sel & (BIT(clock->info[MUX_WIDTH_INFO]) - 1);
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div = mmio_read_32(clock->info[DIV_ADDR_INFO]) >>
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clock->info[DIV_SHIFT_INFO];
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div = div & (BIT(clock->info[DIV_WIDTH_INFO]) - 1);
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parent_rate = clk_scmi_common_get_parent_rate(clock, sel);
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return parent_rate / (div + 1);
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}
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int clk_scmi_common_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
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{
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unsigned long parent_rate, now, best_rate = 0;
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int i = 0, sel_mask, div_mask, best_sel = 0, best_div = 0, div;
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if ((rate == 0) ||
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(clock->info[MUX_WIDTH_INFO] == 0 && clock->info[DIV_WIDTH_INFO] == 0))
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return SCMI_INVALID_PARAMETERS;
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sel_mask = BIT(clock->info[MUX_WIDTH_INFO]) - 1;
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div_mask = BIT(clock->info[DIV_WIDTH_INFO]) - 1;
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if (clock->info[MUX_WIDTH_INFO] == 0) {
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parent_rate = clk_scmi_common_get_parent_rate(clock, 0);
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div = DIV_ROUND_UP(parent_rate, rate);
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if (div > div_mask + 1)
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div = div_mask + 1;
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mmio_write_32(clock->info[DIV_ADDR_INFO],
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BITS_WITH_WMASK(div - 1, div_mask,
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clock->info[DIV_SHIFT_INFO]));
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} else if (clock->info[DIV_WIDTH_INFO] == 0) {
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for (i = 0; i <= sel_mask; i++) {
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parent_rate = clk_scmi_common_get_parent_rate(clock, i);
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now = parent_rate;
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if (abs(rate - now) < abs(rate - best_rate)) {
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best_rate = now;
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best_sel = i;
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}
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}
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if (best_rate == 0)
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best_sel = 0;
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mmio_write_32(clock->info[MUX_ADDR_INFO],
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BITS_WITH_WMASK(best_sel, sel_mask,
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clock->info[MUX_SHIFT_INFO]));
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} else {
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for (i = 0; i <= sel_mask; i++) {
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parent_rate = clk_scmi_common_get_parent_rate(clock, i);
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div = DIV_ROUND_UP(parent_rate, rate);
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if (div > div_mask + 1)
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div = div_mask + 1;
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now = parent_rate / div;
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if (abs(rate - now) < abs(rate - best_rate)) {
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best_rate = now;
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best_div = div;
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best_sel = i;
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}
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}
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if (best_rate == 0) {
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best_div = div_mask + 1;
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best_sel = 0;
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}
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mmio_write_32(clock->info[DIV_ADDR_INFO],
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BITS_WITH_WMASK(div_mask, div_mask,
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clock->info[DIV_SHIFT_INFO]));
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mmio_write_32(clock->info[MUX_ADDR_INFO],
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BITS_WITH_WMASK(best_sel, sel_mask,
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clock->info[MUX_SHIFT_INFO]));
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mmio_write_32(clock->info[DIV_ADDR_INFO],
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BITS_WITH_WMASK(best_div - 1, div_mask,
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clock->info[DIV_SHIFT_INFO]));
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}
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return 0;
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}
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int clk_scmi_common_set_status(rk_scmi_clock_t *clock, bool status)
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{
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mmio_write_32(clock->info[GATE_ADDR_INFO],
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BITS_WITH_WMASK(!status, 0x1U,
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clock->info[GATE_SHIFT_INFO]));
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return 0;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2024, Rockchip, Inc. All rights reserved.
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* Copyright (c) 2025, Rockchip, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -23,11 +23,14 @@ typedef struct rk_scmi_clock {
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char name[SCMI_CLOCK_NAME_LENGTH_MAX];
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uint8_t enable;
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int8_t is_security;
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int8_t is_dynamic_prate;
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uint32_t id;
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uint32_t rate_cnt;
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uint64_t cur_rate;
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uint32_t enable_count;
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const struct rk_clk_ops *clk_ops;
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const unsigned long *parent_table;
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const uint32_t *info;
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unsigned long *rate_table;
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} rk_scmi_clock_t;
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@ -47,4 +50,7 @@ size_t rockchip_scmi_clock_count(unsigned int agent_id);
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rk_scmi_clock_t *rockchip_scmi_get_clock(uint32_t agent_id,
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uint32_t scmi_id);
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unsigned long clk_scmi_common_get_rate(rk_scmi_clock_t *clock);
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int clk_scmi_common_set_rate(rk_scmi_clock_t *clock, unsigned long rate);
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int clk_scmi_common_set_status(rk_scmi_clock_t *clock, bool status);
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#endif /* RK_SCMI_CLOCK_H */
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44
plat/rockchip/rk3576/drivers/dmc/dmc_rk3576.h
Normal file
44
plat/rockchip/rk3576/drivers/dmc/dmc_rk3576.h
Normal file
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@ -0,0 +1,44 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
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*/
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#ifndef __PLAT_ROCKCHIP_DMC_RK3576_H__
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#define __PLAT_ROCKCHIP_DMC_RK3576_H__
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#define MAX_CH_NUM (2)
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#define CTL_PORT_NUM (5)
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/* DDR_GRF Register */
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#define GRF_CH_CON(ch, n) ((((ch) % 2) * 0x100) + ((n) * 4))
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#define DDR_GRF_CH_STATUS16(ch) (0x220 + ((ch) * 0x100))
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#define GRF_DDRPHY_CON(n) (0x530 + ((n) * 4))
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#define GRF_DDRPHY_CON0(ch) (0x530 + (((ch) % 2) * 0x4))
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#define DDR_GRF_COMMON_CON(n) (0x540 + ((n) * 4))
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/* PMUGRF Register */
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#define PMUGRF_OS_REG(n) (0x200 + ((n) * 4))
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struct low_power_st {
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uint32_t pwrctl;
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uint32_t clkgatectl;
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uint32_t dfi_lp_mode_apb;
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uint32_t grf_ddr_con0;
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uint32_t grf_ddr_con1;
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uint32_t grf_ddr_con6;
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uint32_t grf_ddr_con7;
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uint32_t grf_ddr_con9;
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uint32_t grf_ddrphy_con0;
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uint32_t hwlp_0;
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uint32_t hwlp_c;
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uint32_t pcl_pd;
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};
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struct rk3576_dmc_config {
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struct low_power_st low_power[MAX_CH_NUM];
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};
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void dmc_save(void);
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void dmc_restore(void);
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#endif /* __PLAT_ROCKCHIP_DMC_RK3576_H__ */
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191
plat/rockchip/rk3576/drivers/dmc/suspend.c
Normal file
191
plat/rockchip/rk3576/drivers/dmc/suspend.c
Normal file
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@ -0,0 +1,191 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
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*/
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#include <assert.h>
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#include <errno.h>
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#include <arch_helpers.h>
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#include <bl31/bl31.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <dmc_rk3576.h>
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#include <rk3576_def.h>
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#include <soc.h>
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struct rk3576_dmc_config dmc_config;
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/* DDR_PHY */
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#define LP_CON0 0x0018
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#define DFI_LP_CON0 0x0e04
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/* DDR_CTL */
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#define DDRCTL_STAT 0x10014
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#define DDRCTL_PWRCTL 0x10180
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#define DDRCTL_CLKGATECTL 0x1018c
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/* LP_CON0 */
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#define DS_IO_PD BIT(14)
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#define SCHD_HW_CLOCK_GATING_DISABLE BIT(13)
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#define PCL_PD BIT(12)
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#define DQS_ENABLE BIT(10)
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#define WCK_ENABLE BIT(9)
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#define CTRL_DQS_DRV_OFF BIT(8)
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#define CTRL_SCHEDULER_EN BIT(6)
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/* DFI_LP_CON0 0x0e04 */
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#define DFI_LP_MODE_APB BIT(31)
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/* DDRCTL_STAT 0x10014 */
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#define CTL_SELFREF_STATE_SHIFT (12)
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#define CTL_SELFREF_STATE_MASK (0x7 << CTL_SELFREF_STATE_SHIFT)
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#define CTL_NOT_IN_SELF_REFRESH (0x0 << CTL_SELFREF_STATE_SHIFT)
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#define CTL_SELF_REFRESH_1 (0x1 << CTL_SELFREF_STATE_SHIFT)
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#define CTL_SELF_REFRESH_POWER_DOWN (0x2 << CTL_SELFREF_STATE_SHIFT)
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#define CTL_SELF_REFRESH_2 (0x3 << CTL_SELFREF_STATE_SHIFT)
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#define CTL_SELF_REFRESH_DEEP_SLEEP (0x4 << CTL_SELFREF_STATE_SHIFT)
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#define CTL_SELFREF_TYPE_SHIFT (4)
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#define CTL_SELFREF_TYPE_MASK (0x3 << CTL_SELFREF_TYPE_SHIFT)
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#define CTL_SELFREF_NOT_BY_PHY (0x1 << CTL_SELFREF_TYPE_SHIFT)
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#define CTL_SELFREF_NOT_BY_AUTO (0x2 << CTL_SELFREF_TYPE_SHIFT)
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#define CTL_SELFREF_BY_AUTO (0x3 << CTL_SELFREF_TYPE_SHIFT)
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#define CTL_OPERATING_MODE_MASK (0x7)
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#define CTL_OPERATING_MODE_INIT (0x0)
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#define CTL_OPERATING_MODE_NORMAL (0x1)
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#define CTL_OPERATING_MODE_PD (0x2)
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#define CTL_OPERATING_MODE_SR_SRPD (0x3)
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/* DDRCTL_PWRCTL 0x10180 */
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#define CTL_DSM_EN BIT(18)
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#define CTL_STAY_IN_SELFREF BIT(15)
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#define CTL_SELFREF_SW BIT(11)
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#define CTL_EN_DFI_DRAM_CLK_DISABLE BIT(9)
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#define CTL_POWERDOWN_EN_MASK (0xf)
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#define CTL_POWERDOWN_EN_SHIFT (4)
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#define CTL_SELFREF_EN_MASK (0xf)
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#define CTL_SELFREF_EN_SHIFT (0)
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#define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1)
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#define SYS_REG_DEC_CHINFO_V3(reg2, ch) SYS_REG_DEC_CHINFO(reg2, ch)
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#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
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#define SYS_REG_DEC_NUM_CH_V3(reg2) SYS_REG_DEC_NUM_CH(reg2)
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static void exit_low_power(uint32_t ch, struct rk3576_dmc_config *configs)
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{
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/* LP_CON0: [12]pcl_pd */
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configs->low_power[ch].pcl_pd = mmio_read_32(DDRPHY_BASE_CH(0) + LP_CON0) & PCL_PD;
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mmio_clrbits_32(DDRPHY_BASE_CH(ch) + LP_CON0, PCL_PD);
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/* Disable low power activities */
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configs->low_power[ch].pwrctl = mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL);
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mmio_clrbits_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL,
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CTL_DSM_EN | (CTL_POWERDOWN_EN_MASK << CTL_POWERDOWN_EN_SHIFT) |
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(CTL_SELFREF_EN_MASK << CTL_SELFREF_EN_SHIFT));
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while ((mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_STAT) & CTL_OPERATING_MODE_MASK) !=
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CTL_OPERATING_MODE_NORMAL)
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continue;
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/* DDR_GRF_CHA_CON6: [6:0]rd_lat_delay, [14:8]wr_lat_delay, [15]cmd_dly_eq0_en */
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configs->low_power[ch].grf_ddr_con6 =
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mmio_read_32(DDR_GRF_BASE + GRF_CH_CON(ch, 6)) & 0xff7f;
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mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 6), (0x1ul << (15 + 16)));
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/* DDR_GRF_CHA_CON0: [12:8]ddrctl_axi_cg_en */
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configs->low_power[ch].grf_ddr_con0 =
|
||||
mmio_read_32(DDR_GRF_BASE + GRF_CH_CON(ch, 0)) & 0x1f00;
|
||||
mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 0), 0x1f000000);
|
||||
|
||||
/*
|
||||
* DDR_GRF_CHA_CON1:
|
||||
* [15]ddrctl_apb_pclk_cg_en, [12]ddrmon_pclk_cg_en, [7]dfi_scramble_cg_en,
|
||||
* [6]ddrctl_mem_cg_en, [5]bsm_clk_cg_en, [2]ddrctl_core_cg_en, [1]ddrctl_apb_cg_en
|
||||
*/
|
||||
configs->low_power[ch].grf_ddr_con1 =
|
||||
mmio_read_32(DDR_GRF_BASE + GRF_CH_CON(ch, 1)) & 0x90e6;
|
||||
mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 1), 0x90e60000);
|
||||
|
||||
configs->low_power[ch].hwlp_0 = mmio_read_32(HWLP_BASE_CH(ch) + 0x0);
|
||||
mmio_write_32(HWLP_BASE_CH(ch) + 0x0, 0x0);
|
||||
configs->low_power[ch].hwlp_c = mmio_read_32(HWLP_BASE_CH(ch) + 0xc);
|
||||
mmio_write_32(HWLP_BASE_CH(ch) + 0xc, 0x0);
|
||||
|
||||
/* DDR_GRF_CHA_PHY_CON0: [14]ddrphy_pclk_cg_en */
|
||||
configs->low_power[ch].grf_ddrphy_con0 =
|
||||
mmio_read_32(DDR_GRF_BASE + GRF_DDRPHY_CON0(ch)) & BIT(14);
|
||||
mmio_write_32(DDR_GRF_BASE + GRF_DDRPHY_CON0(ch), BIT(14 + 16));
|
||||
|
||||
/* CLKGATECTL: [5:0]bsm_clk_on */
|
||||
configs->low_power[ch].clkgatectl =
|
||||
mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_CLKGATECTL) & 0x3f;
|
||||
/* DFI_LP_CON0: [31]dfi_lp_mode_apb */
|
||||
configs->low_power[ch].dfi_lp_mode_apb =
|
||||
(mmio_read_32(DDRPHY_BASE_CH(ch) + DFI_LP_CON0) >> 31) & 0x1;
|
||||
}
|
||||
|
||||
static void resume_low_power(uint32_t ch, struct rk3576_dmc_config *configs)
|
||||
{
|
||||
/* DFI_LP_CON0: [31]dfi_lp_mode_apb */
|
||||
if (configs->low_power[ch].dfi_lp_mode_apb != 0)
|
||||
mmio_setbits_32(DDRPHY_BASE_CH(ch) + DFI_LP_CON0, DFI_LP_MODE_APB);
|
||||
|
||||
/* CLKGATECTL: [5:0]bsm_clk_on */
|
||||
mmio_clrsetbits_32(UMCTL_BASE_CH(ch) + DDRCTL_CLKGATECTL,
|
||||
0x3f, configs->low_power[ch].clkgatectl & 0x3f);
|
||||
|
||||
/* DDR_GRF_CHA_CON6: [6:0]rd_lat_delay, [14:8]wr_lat_delay, [15]cmd_dly_eq0_en */
|
||||
mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 6),
|
||||
(0xff7ful << 16) | configs->low_power[ch].grf_ddr_con6);
|
||||
|
||||
mmio_write_32(HWLP_BASE_CH(ch) + 0xc, configs->low_power[ch].hwlp_c);
|
||||
mmio_write_32(HWLP_BASE_CH(ch) + 0x0, configs->low_power[ch].hwlp_0);
|
||||
|
||||
/* DDR_GRF_CHA_CON0: [12:8]ddrctl_axi_cg_en */
|
||||
mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 0),
|
||||
(0x1f00ul << 16) | configs->low_power[ch].grf_ddr_con0);
|
||||
|
||||
/*
|
||||
* DDR_GRF_CHA_CON1:
|
||||
* [15]ddrctl_apb_pclk_cg_en, [12]ddrmon_pclk_cg_en, [7]dfi_scramble_cg_en,
|
||||
* [6]ddrctl_mem_cg_en, [5]bsm_clk_cg_en, [2]ddrctl_core_cg_en, [1]ddrctl_apb_cg_en
|
||||
*/
|
||||
mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 1),
|
||||
(0x90e6ul << 16) | configs->low_power[ch].grf_ddr_con1);
|
||||
|
||||
/* DDR_GRF_CHA_PHY_CON0: [14]ddrphy_pclk_cg_en */
|
||||
mmio_write_32(DDR_GRF_BASE + GRF_DDRPHY_CON0(ch),
|
||||
BIT(14 + 16) | configs->low_power[ch].grf_ddrphy_con0);
|
||||
|
||||
/* reset low power activities */
|
||||
mmio_write_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL, configs->low_power[ch].pwrctl);
|
||||
|
||||
/* LP_CON0: [12]pcl_pd */
|
||||
if (configs->low_power[ch].pcl_pd != 0)
|
||||
mmio_setbits_32(DDRPHY_BASE_CH(ch) + LP_CON0, PCL_PD);
|
||||
}
|
||||
|
||||
void dmc_save(void)
|
||||
{
|
||||
uint32_t i, channel_num;
|
||||
|
||||
channel_num =
|
||||
SYS_REG_DEC_NUM_CH_V3(mmio_read_32(PMU1_GRF_BASE + PMUGRF_OS_REG(2)));
|
||||
|
||||
for (i = 0; i < channel_num; i++)
|
||||
exit_low_power(i, &dmc_config);
|
||||
}
|
||||
|
||||
void dmc_restore(void)
|
||||
{
|
||||
uint32_t i, channel_num;
|
||||
|
||||
channel_num = SYS_REG_DEC_NUM_CH_V3(mmio_read_32(PMU1_GRF_BASE + PMUGRF_OS_REG(2)));
|
||||
|
||||
for (i = 0; i < channel_num; i++)
|
||||
resume_low_power(i, &dmc_config);
|
||||
}
|
||||
20
plat/rockchip/rk3576/drivers/pmu/plat_pmu_macros.S
Normal file
20
plat/rockchip/rk3576/drivers/pmu/plat_pmu_macros.S
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <platform_def.h>
|
||||
|
||||
.globl clst_warmboot_data
|
||||
|
||||
.macro func_rockchip_clst_warmboot
|
||||
.endm
|
||||
|
||||
.macro rockchip_clst_warmboot_data
|
||||
clst_warmboot_data:
|
||||
.rept PLATFORM_CLUSTER_COUNT
|
||||
.word 0
|
||||
.endr
|
||||
.endm
|
||||
451
plat/rockchip/rk3576/drivers/pmu/pm_pd_regs.c
Normal file
451
plat/rockchip/rk3576/drivers/pmu/pm_pd_regs.c
Normal file
|
|
@ -0,0 +1,451 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <bl31/bl31.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/console.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <pmu.h>
|
||||
|
||||
#include <plat_pm_helpers.h>
|
||||
#include <plat_private.h>
|
||||
#include <pm_pd_regs.h>
|
||||
#include <rk3576_clk.h>
|
||||
#include <soc.h>
|
||||
|
||||
#define WMSK_VAL 0xffff0000
|
||||
|
||||
static struct reg_region qos_reg_rgns[] = {
|
||||
[qos_decom] = REG_REGION(0x08, 0x18, 4, 0x27f00000, 0),
|
||||
[qos_dmac0] = REG_REGION(0x08, 0x18, 4, 0x27f00080, 0),
|
||||
[qos_dmac1] = REG_REGION(0x08, 0x18, 4, 0x27f00100, 0),
|
||||
[qos_dmac2] = REG_REGION(0x08, 0x18, 4, 0x27f00180, 0),
|
||||
[qos_bus_mcu] = REG_REGION(0x08, 0x18, 4, 0x27f00200, 0),
|
||||
[qos_can0] = REG_REGION(0x08, 0x18, 4, 0x27f00280, 0),
|
||||
[qos_can1] = REG_REGION(0x08, 0x18, 4, 0x27f00300, 0),
|
||||
[qos_cci_m0] = REG_REGION(0x08, 0x18, 4, 0x27f01000, 0),
|
||||
[qos_cci_m1] = REG_REGION(0x08, 0x18, 4, 0x27f18880, 0),
|
||||
[qos_cci_m2] = REG_REGION(0x08, 0x18, 4, 0x27f18900, 0),
|
||||
[qos_dap_lite] = REG_REGION(0x08, 0x18, 4, 0x27f01080, 0),
|
||||
[qos_hdcp1] = REG_REGION(0x08, 0x18, 4, 0x27f02000, 0),
|
||||
[qos_ddr_mcu] = REG_REGION(0x08, 0x18, 4, 0x27f03000, 0),
|
||||
[qos_fspi1] = REG_REGION(0x08, 0x18, 4, 0x27f04000, 0),
|
||||
[qos_gmac0] = REG_REGION(0x08, 0x18, 4, 0x27f04080, 0),
|
||||
[qos_gmac1] = REG_REGION(0x08, 0x18, 4, 0x27f04100, 0),
|
||||
[qos_sdio] = REG_REGION(0x08, 0x18, 4, 0x27f04180, 0),
|
||||
[qos_sdmmc] = REG_REGION(0x08, 0x18, 4, 0x27f04200, 0),
|
||||
[qos_flexbus] = REG_REGION(0x08, 0x18, 4, 0x27f04280, 0),
|
||||
[qos_gpu] = REG_REGION(0x08, 0x18, 4, 0x27f05000, 0),
|
||||
[qos_vepu1] = REG_REGION(0x08, 0x18, 4, 0x27f06000, 0),
|
||||
[qos_npu_mcu] = REG_REGION(0x08, 0x18, 4, 0x27f08000, 0),
|
||||
[qos_npu_nsp0] = REG_REGION(0x08, 0x18, 4, 0x27f08080, 0),
|
||||
[qos_npu_nsp1] = REG_REGION(0x08, 0x18, 4, 0x27f08100, 0),
|
||||
[qos_npu_m0] = REG_REGION(0x08, 0x18, 4, 0x27f20000, 0),
|
||||
[qos_npu_m1] = REG_REGION(0x08, 0x18, 4, 0x27f21000, 0),
|
||||
[qos_npu_m0ro] = REG_REGION(0x08, 0x18, 4, 0x27f22080, 0),
|
||||
[qos_npu_m1ro] = REG_REGION(0x08, 0x18, 4, 0x27f22100, 0),
|
||||
[qos_emmc] = REG_REGION(0x08, 0x18, 4, 0x27f09000, 0),
|
||||
[qos_fspi0] = REG_REGION(0x08, 0x18, 4, 0x27f09080, 0),
|
||||
[qos_mmu0] = REG_REGION(0x08, 0x18, 4, 0x27f0a000, 0),
|
||||
[qos_mmu1] = REG_REGION(0x08, 0x18, 4, 0x27f0a080, 0),
|
||||
[qos_pmu_mcu] = REG_REGION(0x08, 0x18, 4, 0x27f0b000, 0),
|
||||
[qos_rkvdec] = REG_REGION(0x08, 0x18, 4, 0x27f0c000, 0),
|
||||
[qos_crypto] = REG_REGION(0x08, 0x18, 4, 0x27f0d000, 0),
|
||||
[qos_mmu2] = REG_REGION(0x08, 0x18, 4, 0x27f0e000, 0),
|
||||
[qos_ufshc] = REG_REGION(0x08, 0x18, 4, 0x27f0e080, 0),
|
||||
[qos_vepu0] = REG_REGION(0x08, 0x18, 4, 0x27f0f000, 0),
|
||||
[qos_isp_mro] = REG_REGION(0x08, 0x18, 4, 0x27f10000, 0),
|
||||
[qos_isp_mwo] = REG_REGION(0x08, 0x18, 4, 0x27f10080, 0),
|
||||
[qos_vicap_m0] = REG_REGION(0x08, 0x18, 4, 0x27f10100, 0),
|
||||
[qos_vpss_mro] = REG_REGION(0x08, 0x18, 4, 0x27f10180, 0),
|
||||
[qos_vpss_mwo] = REG_REGION(0x08, 0x18, 4, 0x27f10200, 0),
|
||||
[qos_hdcp0] = REG_REGION(0x08, 0x18, 4, 0x27f11000, 0),
|
||||
[qos_vop_m0] = REG_REGION(0x08, 0x18, 4, 0x27f12800, 0),
|
||||
[qos_vop_m1ro] = REG_REGION(0x08, 0x18, 4, 0x27f12880, 0),
|
||||
[qos_ebc] = REG_REGION(0x08, 0x18, 4, 0x27f13000, 0),
|
||||
[qos_rga0] = REG_REGION(0x08, 0x18, 4, 0x27f13080, 0),
|
||||
[qos_rga1] = REG_REGION(0x08, 0x18, 4, 0x27f13100, 0),
|
||||
[qos_jpeg] = REG_REGION(0x08, 0x18, 4, 0x27f13180, 0),
|
||||
[qos_vdpp] = REG_REGION(0x08, 0x18, 4, 0x27f13200, 0),
|
||||
[qos_dma2ddr] = REG_REGION(0x08, 0x18, 4, 0x27f15880, 0),
|
||||
};
|
||||
|
||||
static struct reg_region pd_bcore_reg_rgns[] = {
|
||||
/* bcore cru */
|
||||
/* REG_REGION(0x280, 0x280, 4, BIGCORE0CRU_BASE, WMSK_VAL), */
|
||||
REG_REGION(0x300, 0x30c, 4, BIGCORE_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0x800, 0x804, 4, BIGCORE_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0xa00, 0xa0c, 4, BIGCORE_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0xcc0, 0xcc0, 4, BIGCORE_CRU_BASE, 0),
|
||||
REG_REGION(0xf28, 0xf28, 8, BIGCORE_CRU_BASE, 0),
|
||||
REG_REGION(0xf2c, 0xf2c, 8, BIGCORE_CRU_BASE, WMSK_VAL),
|
||||
|
||||
/* bcore_grf */
|
||||
REG_REGION(0x34, 0x3c, 4, BIGCORE_GRF_BASE, WMSK_VAL),
|
||||
REG_REGION(0x44, 0x44, 4, BIGCORE_GRF_BASE, WMSK_VAL),
|
||||
};
|
||||
|
||||
static struct reg_region pd_core_reg_rgns[] = {
|
||||
/* cci cru */
|
||||
REG_REGION(0x310, 0x310, 4, CCI_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0x804, 0x808, 4, CCI_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0xa04, 0xa08, 4, CCI_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0xc50, 0xc58, 4, CCI_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0xd00, 0xd00, 8, CCI_CRU_BASE, 0),
|
||||
REG_REGION(0xd04, 0xd04, 8, CCI_CRU_BASE, WMSK_VAL),
|
||||
/* Restore lpll registers after clksel_* registers. Because lpll
|
||||
* may be turned off during restoring, which cause cci_cru to lost clock.
|
||||
*/
|
||||
REG_REGION(0x040, 0x044, 4, CCI_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0x048, 0x048, 4, CCI_CRU_BASE, 0),
|
||||
REG_REGION(0x04c, 0x058, 4, CCI_CRU_BASE, WMSK_VAL),
|
||||
|
||||
/* lcore cru */
|
||||
/* REG_REGION(0x280, 0x280, 4, BIGCORE1CRU_BASE, WMSK_VAL), */
|
||||
REG_REGION(0x300, 0x30c, 4, LITTLE_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0x800, 0x804, 4, LITTLE_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0xa00, 0xa0c, 4, LITTLE_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0xcc0, 0xcc0, 4, LITTLE_CRU_BASE, 0),
|
||||
REG_REGION(0xf38, 0xf38, 8, LITTLE_CRU_BASE, 0),
|
||||
REG_REGION(0xf3c, 0xf3c, 8, LITTLE_CRU_BASE, WMSK_VAL),
|
||||
|
||||
/* bcore cru */
|
||||
/* REG_REGION(0x280, 0x280, 4, BIGCORE0CRU_BASE, WMSK_VAL), */
|
||||
REG_REGION(0x300, 0x30c, 4, BIGCORE_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0x800, 0x804, 4, BIGCORE_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0xa00, 0xa0c, 4, BIGCORE_CRU_BASE, WMSK_VAL),
|
||||
REG_REGION(0xcc0, 0xcc0, 4, BIGCORE_CRU_BASE, 0),
|
||||
REG_REGION(0xf28, 0xf28, 8, BIGCORE_CRU_BASE, 0),
|
||||
REG_REGION(0xf2c, 0xf2c, 8, BIGCORE_CRU_BASE, WMSK_VAL),
|
||||
|
||||
/* cci grf */
|
||||
REG_REGION(0x00, 0x10, 4, CCI_GRF_BASE, WMSK_VAL),
|
||||
REG_REGION(0x54, 0x54, 4, CCI_GRF_BASE, WMSK_VAL),
|
||||
|
||||
/* lcore_grf */
|
||||
REG_REGION(0x34, 0x3c, 4, LITCORE_GRF_BASE, WMSK_VAL),
|
||||
REG_REGION(0x44, 0x44, 4, LITCORE_GRF_BASE, WMSK_VAL),
|
||||
|
||||
/* bcore_grf */
|
||||
REG_REGION(0x34, 0x3c, 4, BIGCORE_GRF_BASE, WMSK_VAL),
|
||||
REG_REGION(0x44, 0x44, 4, BIGCORE_GRF_BASE, WMSK_VAL),
|
||||
};
|
||||
|
||||
static struct reg_region pd_php_reg_rgns[] = {
|
||||
/* php_grf */
|
||||
REG_REGION(0x004, 0x00c, 4, PHP_GRF_BASE, WMSK_VAL),
|
||||
REG_REGION(0x010, 0x018, 4, PHP_GRF_BASE, 0),
|
||||
REG_REGION(0x01c, 0x020, 4, PHP_GRF_BASE, WMSK_VAL),
|
||||
REG_REGION(0x048, 0x048, 4, PHP_GRF_BASE, 0),
|
||||
};
|
||||
|
||||
static struct reg_region pd_usb2phy_reg_rgns[] = {
|
||||
/* usb */
|
||||
REG_REGION(0x00, 0x14, 4, USB2PHY0_GRF_BASE, WMSK_VAL),
|
||||
REG_REGION(0x40, 0x40, 4, USB2PHY0_GRF_BASE, WMSK_VAL),
|
||||
REG_REGION(0x44, 0x50, 4, USB2PHY0_GRF_BASE, 0),
|
||||
REG_REGION(0x00, 0x14, 4, USB2PHY1_GRF_BASE, WMSK_VAL),
|
||||
REG_REGION(0x08, 0x08, 4, USBDPPHY_GRF_BASE, WMSK_VAL),
|
||||
};
|
||||
|
||||
#define PLL_LOCKED_TIMEOUT 600000U
|
||||
|
||||
static void pm_pll_wait_lock(uint32_t pll_base)
|
||||
{
|
||||
int delay = PLL_LOCKED_TIMEOUT;
|
||||
|
||||
if ((mmio_read_32(pll_base + CRU_PLL_CON(1)) & CRU_PLLCON1_PWRDOWN) != 0)
|
||||
return;
|
||||
|
||||
while (delay-- >= 0) {
|
||||
if ((mmio_read_32(pll_base + CRU_PLL_CON(6)) & CRU_PLLCON6_LOCK_STATUS) != 0)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (delay <= 0)
|
||||
ERROR("Can't wait pll(0x%x) lock\n", pll_base);
|
||||
}
|
||||
|
||||
void qos_save(void)
|
||||
{
|
||||
uint32_t pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_nvm)) == 0) {
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_emmc], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_fspi0], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_sd_gmac)) == 0) {
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_fspi1], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_gmac0], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_gmac1], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_sdio], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_sdmmc], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_flexbus], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_php)) == 0) {
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_mmu0], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_mmu1], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vop)) == 0) {
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_vop_m0], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_vop_m1ro], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vo1)) == 0)
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_hdcp1], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vo0)) == 0)
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_hdcp0], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_usb)) == 0) {
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_mmu2], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_ufshc], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vi)) == 0) {
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_isp_mro], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_isp_mwo], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_vicap_m0], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_vpss_mro], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_vpss_mwo], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vepu0)) == 0)
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_vepu0], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vepu1)) == 0)
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_vepu1], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vdec)) == 0)
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_rkvdec], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vpu)) == 0) {
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_ebc], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_rga0], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_rga1], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_jpeg], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_vdpp], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_nputop)) == 0) {
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_mcu], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_nsp0], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_nsp1], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_m0ro], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_m1ro], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_npu0)) == 0)
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_m0], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_npu1)) == 0)
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_m1], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_gpu)) == 0)
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_gpu], 1);
|
||||
}
|
||||
|
||||
void qos_restore(void)
|
||||
{
|
||||
uint32_t pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_nvm)) == 0) {
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_emmc], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_fspi0], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_sd_gmac)) == 0) {
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_fspi1], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_gmac0], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_gmac1], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_sdio], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_sdmmc], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_flexbus], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_php)) == 0) {
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_mmu0], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_mmu1], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vop)) == 0) {
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vop_m0], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vop_m1ro], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vo1)) == 0)
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_hdcp1], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vo0)) == 0)
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_hdcp0], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_usb)) == 0) {
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_mmu2], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_ufshc], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vi)) == 0) {
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_isp_mro], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_isp_mwo], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vicap_m0], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vpss_mro], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vpss_mwo], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vepu0)) == 0)
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vepu0], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vepu1)) == 0)
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vepu1], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vdec)) == 0)
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_rkvdec], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_vpu)) == 0) {
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_ebc], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_rga0], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_rga1], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_jpeg], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vdpp], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_nputop)) == 0) {
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_mcu], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_nsp0], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_nsp1], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_m0ro], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_m1ro], 1);
|
||||
}
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_npu0)) == 0)
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_m0], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_npu1)) == 0)
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_m1], 1);
|
||||
|
||||
if ((pmu_pd_st & BIT(pmu_pd_gpu)) == 0)
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_gpu], 1);
|
||||
}
|
||||
|
||||
void pd_usb2phy_save(void)
|
||||
{
|
||||
rockchip_reg_rgn_save(pd_usb2phy_reg_rgns, ARRAY_SIZE(pd_usb2phy_reg_rgns));
|
||||
}
|
||||
|
||||
void pd_usb2phy_restore(void)
|
||||
{
|
||||
rockchip_reg_rgn_restore(pd_usb2phy_reg_rgns, ARRAY_SIZE(pd_usb2phy_reg_rgns));
|
||||
}
|
||||
|
||||
static uint32_t b_cru_mode, l_cru_mode;
|
||||
static uint32_t bcore_need_restore;
|
||||
|
||||
void pd_bcore_save(void)
|
||||
{
|
||||
pvtplls_cpub_suspend();
|
||||
|
||||
b_cru_mode = mmio_read_32(BIGCORE_CRU_BASE + 0x280);
|
||||
rockchip_reg_rgn_save(pd_bcore_reg_rgns, ARRAY_SIZE(pd_bcore_reg_rgns));
|
||||
|
||||
bcore_need_restore = 1;
|
||||
}
|
||||
|
||||
void pd_bcore_restore(void)
|
||||
{
|
||||
if (bcore_need_restore == 0)
|
||||
return;
|
||||
|
||||
/* slow mode */
|
||||
mmio_write_32(BIGCORE_CRU_BASE + 0x280, 0x00030000);
|
||||
|
||||
rockchip_reg_rgn_restore(pd_bcore_reg_rgns, ARRAY_SIZE(pd_bcore_reg_rgns));
|
||||
|
||||
/* trigger lcore/bcore mem_cfg */
|
||||
mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(1, 0x1, 1));
|
||||
udelay(1);
|
||||
mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(0, 0x1, 1));
|
||||
|
||||
/* restore mode */
|
||||
mmio_write_32(BIGCORE_CRU_BASE + 0x280, WITH_16BITS_WMSK(b_cru_mode));
|
||||
|
||||
pvtplls_cpub_resume();
|
||||
|
||||
bcore_need_restore = 0;
|
||||
}
|
||||
|
||||
void pd_core_save(void)
|
||||
{
|
||||
pvtplls_suspend();
|
||||
|
||||
b_cru_mode = mmio_read_32(BIGCORE_CRU_BASE + 0x280);
|
||||
l_cru_mode = mmio_read_32(LITTLE_CRU_BASE + 0x280);
|
||||
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_cci_m0], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_cci_m1], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_cci_m2], 1);
|
||||
rockchip_reg_rgn_save(&qos_reg_rgns[qos_dap_lite], 1);
|
||||
|
||||
rockchip_reg_rgn_save(pd_core_reg_rgns, ARRAY_SIZE(pd_core_reg_rgns));
|
||||
}
|
||||
|
||||
void pd_core_restore(void)
|
||||
{
|
||||
/* slow mode */
|
||||
mmio_write_32(BIGCORE_CRU_BASE + 0x280, 0x00030000);
|
||||
mmio_write_32(LITTLE_CRU_BASE + 0x280, 0x00030000);
|
||||
|
||||
rockchip_reg_rgn_restore(pd_core_reg_rgns, ARRAY_SIZE(pd_core_reg_rgns));
|
||||
|
||||
/* trigger lcore/bcore mem_cfg */
|
||||
mmio_write_32(LITCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(1, 0x1, 1));
|
||||
mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(1, 0x1, 1));
|
||||
udelay(1);
|
||||
mmio_write_32(LITCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(0, 0x1, 1));
|
||||
mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(0, 0x1, 1));
|
||||
|
||||
/* wait lock */
|
||||
pm_pll_wait_lock(CCI_CRU_BASE + 0x40);
|
||||
|
||||
/* restore mode */
|
||||
mmio_write_32(BIGCORE_CRU_BASE + 0x280, WITH_16BITS_WMSK(b_cru_mode));
|
||||
mmio_write_32(LITTLE_CRU_BASE + 0x280, WITH_16BITS_WMSK(l_cru_mode));
|
||||
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_cci_m0], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_cci_m1], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_cci_m2], 1);
|
||||
rockchip_reg_rgn_restore(&qos_reg_rgns[qos_dap_lite], 1);
|
||||
|
||||
pvtplls_resume();
|
||||
}
|
||||
|
||||
void pd_php_save(void)
|
||||
{
|
||||
rockchip_reg_rgn_save(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns));
|
||||
}
|
||||
|
||||
void pd_php_restore(void)
|
||||
{
|
||||
rockchip_reg_rgn_restore(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns));
|
||||
}
|
||||
|
||||
void pm_reg_rgns_init(void)
|
||||
{
|
||||
rockchip_alloc_region_mem(qos_reg_rgns, ARRAY_SIZE(qos_reg_rgns));
|
||||
rockchip_alloc_region_mem(pd_bcore_reg_rgns, ARRAY_SIZE(pd_bcore_reg_rgns));
|
||||
rockchip_alloc_region_mem(pd_core_reg_rgns, ARRAY_SIZE(pd_core_reg_rgns));
|
||||
rockchip_alloc_region_mem(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns));
|
||||
rockchip_alloc_region_mem(pd_usb2phy_reg_rgns, ARRAY_SIZE(pd_usb2phy_reg_rgns));
|
||||
}
|
||||
36
plat/rockchip/rk3576/drivers/pmu/pm_pd_regs.h
Normal file
36
plat/rockchip/rk3576/drivers/pmu/pm_pd_regs.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef PM_PD_REGS_H
|
||||
#define PM_PD_REGS_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void qos_save(void);
|
||||
void qos_restore(void);
|
||||
void pd_usb2phy_save(void);
|
||||
void pd_usb2phy_restore(void);
|
||||
void pd_secure_save(void);
|
||||
void pd_secure_restore(void);
|
||||
void pd_bcore_save(void);
|
||||
void pd_bcore_restore(void);
|
||||
void pd_core_save(void);
|
||||
void pd_core_restore(void);
|
||||
void pd_php_save(void);
|
||||
void pd_php_restore(void);
|
||||
void pd_center_save(void);
|
||||
void pd_center_restore(void);
|
||||
void pd_bus_save(void);
|
||||
void pd_bus_restore(void);
|
||||
void pd_pmu1_save(void);
|
||||
void pd_pmu1_restore_early(void);
|
||||
void pd_pmu1_restore(void);
|
||||
void pd_pmu0_save(void);
|
||||
void pd_pmu0_restore(void);
|
||||
|
||||
void pm_reg_rgns_init(void);
|
||||
void pm_regs_rgn_dump(void);
|
||||
|
||||
#endif
|
||||
1069
plat/rockchip/rk3576/drivers/pmu/pmu.c
Normal file
1069
plat/rockchip/rk3576/drivers/pmu/pmu.c
Normal file
File diff suppressed because it is too large
Load diff
578
plat/rockchip/rk3576/drivers/pmu/pmu.h
Normal file
578
plat/rockchip/rk3576/drivers/pmu/pmu.h
Normal file
|
|
@ -0,0 +1,578 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __PMU_H__
|
||||
#define __PMU_H__
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <mmio.h>
|
||||
|
||||
/* PMU */
|
||||
#define PMU1_OFFSET 0x10000
|
||||
#define PMU2_OFFSET 0x20000
|
||||
|
||||
#define PMU0_PWR_CON 0x0000
|
||||
#define PMU0_PWR_STATUS 0x0004
|
||||
#define PMU0_WAKEUP_INT_CON 0x0008
|
||||
#define PMU0_WAKEUP_INT_ST 0x000c
|
||||
#define PMU0_PMIC_STABLE_CNT_THRES 0x0010
|
||||
#define PMU0_WAKEUP_RST_CLR_CNT_THRES 0x0014
|
||||
#define PMU0_OSC_STABLE_CNT_THRES 0x0018
|
||||
#define PMU0_PWR_C0_STABLE_CON 0x001c
|
||||
#define PMU0_DDR_RET_CON(i) (0x0020 + (i) * 4)
|
||||
#define PMU0_INFO_TX_CON 0x0030
|
||||
|
||||
#define PMU1_VERSION_ID (PMU1_OFFSET + 0x0000)
|
||||
#define PMU1_PWR_CON (PMU1_OFFSET + 0x0004)
|
||||
#define PMU1_PWR_FSM (PMU1_OFFSET + 0x0008)
|
||||
#define PMU1_INT_MASK_CON (PMU1_OFFSET + 0x000c)
|
||||
#define PMU1_WAKEUP_INT_CON (PMU1_OFFSET + 0x0010)
|
||||
#define PMU1_WAKEUP_INT_ST (PMU1_OFFSET + 0x0014)
|
||||
#define PMU1_DDR_PWR_CON(i) (PMU1_OFFSET + 0x0100 + (i) * 4)
|
||||
#define PMU1_DDR_PWR_SFTCON(i) (PMU1_OFFSET + 0x0110 + (i) * 4)
|
||||
#define PMU1_DDR_AXIPWR_CON(i) (PMU1_OFFSET + 0x0120 + (i) * 4)
|
||||
#define PMU1_DDR_AXIPWR_SFTCON(i) (PMU1_OFFSET + 0x0130 + (i) * 4)
|
||||
#define PMU1_DDR_PWR_FSM (PMU1_OFFSET + 0x0140)
|
||||
#define PMU1_DDR_PWR_ST (PMU1_OFFSET + 0x0144)
|
||||
#define PMU1_DDR_AXIPWR_ST (PMU1_OFFSET + 0x0148)
|
||||
#define PMU1_CRU_PWR_CON(i) (PMU1_OFFSET + 0x0200 + (i) * 4)
|
||||
#define PMU1_CRU_PWR_SFTCON(i) (PMU1_OFFSET + 0x0208 + (i) * 4)
|
||||
#define PMU1_CRU_PWR_FSM (PMU1_OFFSET + 0x0210)
|
||||
#define PMU1_PLLPD_CON(i) (PMU1_OFFSET + 0x0220 + (i) * 4)
|
||||
#define PMU1_PLLPD_SFTCON(i) (PMU1_OFFSET + 0x0228 + (i) * 4)
|
||||
#define PMU1_STABLE_CNT_THRESH (PMU1_OFFSET + 0x0300)
|
||||
#define PMU1_OSC_STABLE_CNT_THRESH (PMU1_OFFSET + 0x0304)
|
||||
#define PMU1_WAKEUP_RST_CLR_CNT_THRESH (PMU1_OFFSET + 0x0308)
|
||||
#define PMU1_PLL_LOCK_CNT_THRESH (PMU1_OFFSET + 0x030c)
|
||||
#define PMU1_WAKEUP_TIMEOUT_THRESH (PMU1_OFFSET + 0x0310)
|
||||
#define PMU1_PWM_SWITCH_CNT_THRESH (PMU1_OFFSET + 0x0314)
|
||||
#define PMU1_SLEEP_CNT_THRESH (PMU1_OFFSET + 0x0318)
|
||||
#define PMU1_INFO_TX_CON (PMU1_OFFSET + 0x0400)
|
||||
|
||||
#define PMU2_SCU0_PWR_CON (PMU2_OFFSET + 0x0000)
|
||||
#define PMU2_SCU1_PWR_CON (PMU2_OFFSET + 0x0004)
|
||||
#define PMU2_SCU0_PWR_SFTCON (PMU2_OFFSET + 0x0008)
|
||||
#define PMU2_SCU1_PWR_SFTCON (PMU2_OFFSET + 0x000c)
|
||||
#define PMU2_SCU0_AUTO_PWR_CON (PMU2_OFFSET + 0x0010)
|
||||
#define PMU2_SCU1_AUTO_PWR_CON (PMU2_OFFSET + 0x0014)
|
||||
#define PMU2_SCU_PWR_FSM_STATUS (PMU2_OFFSET + 0x0018)
|
||||
#define PMU2_DBG_PWR_CON(i) (PMU2_OFFSET + 0x001c + (i) * 4)
|
||||
#define PMU2_CLUSTER_PWR_ST (PMU2_OFFSET + 0x0024)
|
||||
#define PMU2_CLUSTER0_IDLE_CON (PMU2_OFFSET + 0x0028)
|
||||
#define PMU2_CLUSTER1_IDLE_CON (PMU2_OFFSET + 0x002c)
|
||||
#define PMU2_CLUSTER0_IDLE_SFTCON (PMU2_OFFSET + 0x0030)
|
||||
#define PMU2_CLUSTER1_IDLE_SFTCON (PMU2_OFFSET + 0x0034)
|
||||
#define PMU2_CLUSTER_IDLE_ACK (PMU2_OFFSET + 0x0038)
|
||||
#define PMU2_CLUSTER_IDLE_ST (PMU2_OFFSET + 0x003c)
|
||||
#define PMU2_SCU0_PWRUP_CNT_THRESH (PMU2_OFFSET + 0x0040)
|
||||
#define PMU2_SCU0_PWRDN_CNT_THRESH (PMU2_OFFSET + 0x0044)
|
||||
#define PMU2_SCU0_STABLE_CNT_THRESH (PMU2_OFFSET + 0x0048)
|
||||
#define PMU2_SCU1_PWRUP_CNT_THRESH (PMU2_OFFSET + 0x004c)
|
||||
#define PMU2_SCU1_PWRDN_CNT_THRESH (PMU2_OFFSET + 0x0050)
|
||||
#define PMU2_SCU1_STABLE_CNT_THRESH (PMU2_OFFSET + 0x0054)
|
||||
#define PMU2_CPU_AUTO_PWR_CON(i) (PMU2_OFFSET + 0x0080 + ((i)) * 4)
|
||||
#define PMU2_CPU_PWR_SFTCON(i) (PMU2_OFFSET + 0x00a0 + ((i)) * 4)
|
||||
#define PMU2_CCI_PWR_CON (PMU2_OFFSET + 0x00e0)
|
||||
#define PMU2_CCI_PWR_SFTCON (PMU2_OFFSET + 0x00e4)
|
||||
#define PMU2_CCI_PWR_ST (PMU2_OFFSET + 0x00e8)
|
||||
#define PMU2_CCI_POWER_STATE (PMU2_OFFSET + 0x00ec)
|
||||
#define PMU2_BUS_IDLE_CON(i) (PMU2_OFFSET + 0x0100 + (i) * 4)
|
||||
#define PMU2_BUS_IDLE_SFTCON(i) (PMU2_OFFSET + 0x0110 + (i) * 4)
|
||||
#define PMU2_BUS_IDLE_ACK (PMU2_OFFSET + 0x0120)
|
||||
#define PMU2_BUS_IDLE_ST (PMU2_OFFSET + 0x0128)
|
||||
#define PMU2_NOC_AUTO_CON(i) (PMU2_OFFSET + 0x0130 + (i) * 4)
|
||||
#define PMU2_NOC_AUTO_SFTCON(i) (PMU2_OFFSET + 0x0140 + (i) * 4)
|
||||
#define PMU2_BUS_IDLEACK_BYPASS_CON (PMU2_OFFSET + 0x0150)
|
||||
#define PMU2_PWR_GATE_CON(i) (PMU2_OFFSET + 0x0200 + (i) * 4)
|
||||
#define PMU2_PWR_GATE_SFTCON(i) (PMU2_OFFSET + 0x0210 + (i) * 4)
|
||||
#define PMU2_VOL_GATE_SFTCON(i) (PMU2_OFFSET + 0x0220 + (i) * 4)
|
||||
#define PMU2_PWR_GATE_ST (PMU2_OFFSET + 0x0230)
|
||||
#define PMU2_PWR_GATE_FSM (PMU2_OFFSET + 0x0238)
|
||||
#define PMU2_PD_DWN_ACK_STATE(i) (PMU2_OFFSET + 0x0240 + (i) * 4)
|
||||
#define PMU2_PD_DWN_LC_ACK_STATE(i) (PMU2_OFFSET + 0x0248 + (i) * 4)
|
||||
#define PMU2_PD_DWN_MEM_ACK_STATE(i) (PMU2_OFFSET + 0x0250 + (i) * 4)
|
||||
#define PMU2_PWR_UP_C0_STABLE_CON(i) (PMU2_OFFSET + 0x0260 + (i) * 4)
|
||||
#define PMU2_PWR_DWN_C0_STABLE_CON(i) (PMU2_OFFSET + 0x0270 + (i) * 4)
|
||||
#define PMU2_PWR_STABLE_C0_CNT_THRES (PMU2_OFFSET + 0x027c)
|
||||
#define PMU2_FAST_POWER_CON (PMU2_OFFSET + 0x0284)
|
||||
#define PMU2_FAST_PWRUP_CNT_THRESH_0 (PMU2_OFFSET + 0x0288)
|
||||
#define PMU2_FAST_PWRDN_CNT_THRESH_0 (PMU2_OFFSET + 0x028c)
|
||||
#define PMU2_FAST_PWRUP_CNT_THRESH_1 (PMU2_OFFSET + 0x0290)
|
||||
#define PMU2_FAST_PWRDN_CNT_THRESH_1 (PMU2_OFFSET + 0x0294)
|
||||
#define PMU2_FAST_PWRUP_CNT_THRESH_2 (PMU2_OFFSET + 0x0298)
|
||||
#define PMU2_FAST_PWRDN_CNT_THRESH_2 (PMU2_OFFSET + 0x029c)
|
||||
#define PMU2_MEM_PWR_GATE_SFTCON(i) (PMU2_OFFSET + 0x0300)
|
||||
#define PMU2_SUBMEM_PWR_GATE_SFTCON(i) (PMU2_OFFSET + 0x0310)
|
||||
#define PMU2_SUBMEM_PWR_ACK_BYPASS_SFTCON(i) (PMU2_OFFSET + 0x0320)
|
||||
#define PMU2_SUBMEM_PWR_GATE_STATUS (PMU2_OFFSET + 0x0328)
|
||||
#define PMU2_QCHANNEL_PWR_CON0 (PMU2_OFFSET + 0x0400)
|
||||
#define PMU2_QCHANNEL_PWR_SFTCON0 (PMU2_OFFSET + 0x0404)
|
||||
#define PMU2_QCHANNEL_STATUS0 (PMU2_OFFSET + 0x0408)
|
||||
#define PMU2_C0_PWRACK_BYPASS_CON(i) (PMU2_OFFSET + 0x0380 + (i) * 4)
|
||||
#define PMU2_C1_PWRACK_BYPASS_CON(i) (PMU2_OFFSET + 0x0390 + (i) * 4)
|
||||
#define PMU2_C2_PWRACK_BYPASS_CON(i) (PMU2_OFFSET + 0x03a0 + (i) * 4)
|
||||
#define PMU2_DEBUG_INFO_SEL (PMU2_OFFSET + 0x03f0)
|
||||
#define PMU2_BISR_GLB_CON (PMU2_OFFSET + 0x500)
|
||||
#define PMU2_BISR_TIMEOUT_THRES (PMU2_OFFSET + 0x504)
|
||||
#define PMU2_BISR_PDGEN_CON(i) (PMU2_OFFSET + 0x510 + (i) * 4)
|
||||
#define PMU2_BISR_PDGEN_SFTCON(i) (PMU2_OFFSET + 0x520 + (i) * 4)
|
||||
#define PMU2_BISR_PDGDONE_CON(i) (PMU2_OFFSET + 0x530 + (i) * 4)
|
||||
#define PMU2_BISR_PDGINIT_CON(i) (PMU2_OFFSET + 0x540 + (i) * 4)
|
||||
#define PMU2_BISR_PDGDONE_STATUS(i) (PMU2_OFFSET + 0x550 + (i) * 4)
|
||||
#define PMU2_BISR_PDGCEDIS_STATUS(i) (PMU2_OFFSET + 0x560 + (i) * 4)
|
||||
#define PMU2_BISR_PWR_REPAIR_STATUS(i) (PMU2_OFFSET + 0x570 + (i) * 4)
|
||||
|
||||
/* PMU1CRU */
|
||||
#define PMU1CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
|
||||
#define PMU1CRU_CLKSEL_CON_CNT 22
|
||||
#define PMU1CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
|
||||
#define PMU1CRU_CLKGATE_CON_CNT 8
|
||||
#define PMU1CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
|
||||
#define PMU1CRU_SOFTRST_CON_CNT 8
|
||||
#define PMU1CRU_DEEPSLOW_DET_CON 0xb40
|
||||
#define PMU1CRU_DEEPSLOW_DET_ST 0xb44
|
||||
|
||||
/* PMU1SCRU */
|
||||
#define PMU1SCRU_CLKSEL_CON(i) ((i) * 0x4 + 0x4000)
|
||||
#define PMU1SCRU_CLKSEL_CON_CNT 3
|
||||
#define PMU1SCRU_CLKGATE_CON(i) ((i) * 0x4 + 0x4028)
|
||||
#define PMU1SCRU_CLKGATE_CON_CNT 3
|
||||
#define PMU1SCRU_SOFTRST_CON(i) ((i) * 0x4 + 0x4050)
|
||||
#define PMU1SCRU_SOFTRST_CONCNT 3
|
||||
|
||||
/* PMU0GRF */
|
||||
#define PMU0GRF_SOC_CON(i) ((i) * 4)
|
||||
#define PMU0GRF_IO_RET_CON(i) (0x20 + (i) * 4)
|
||||
#define PMU0GRF_OS_REG(i) ((i) * 4)
|
||||
|
||||
/* PMU1GRF */
|
||||
#define PMU1GRF_SOC_CON(i) ((i) * 4)
|
||||
#define PMU1GRF_SOC_ST 0x60
|
||||
#define PMU1GRF_MEM_CON(i) (0x80 + (i) * 4)
|
||||
#define PMU1GRF_OS_REG(i) (0x200 + (i) * 4)
|
||||
|
||||
#define PMU_MCU_HALT BIT(7)
|
||||
#define PMU_MCU_SLEEP BIT(9)
|
||||
#define PMU_MCU_DEEPSLEEP BIT(10)
|
||||
#define PMU_MCU_STOP_MSK \
|
||||
(PMU_MCU_HALT | PMU_MCU_SLEEP | PMU_MCU_DEEPSLEEP)
|
||||
|
||||
#define CORES_PM_DISABLE 0x0
|
||||
|
||||
/* pmuioc */
|
||||
#define PMUIO0_IOC_GPIO0A_IOMUX_SEL_L 0x000
|
||||
#define PMUIO0_IOC_GPIO0A_IOMUX_SEL_H 0x004
|
||||
#define PMUIO0_IOC_GPIO0B_IOMUX_SEL_L 0x008
|
||||
|
||||
#define PMUIO1_IOC_GPIO0B_IOMUX_SEL_H 0x000
|
||||
#define PMUIO1_IOC_GPIO0C_IOMUX_SEL_L 0x004
|
||||
#define PMUIO1_IOC_GPIO0C_IOMUX_SEL_H 0x008
|
||||
#define PMUIO1_IOC_GPIO0D_IOMUX_SEL_L 0x00c
|
||||
#define PMUIO1_IOC_GPIO0D_IOMUX_SEL_H 0x010
|
||||
|
||||
/* PMU_PWR_CON */
|
||||
enum pmu0_pwr_con {
|
||||
pmu_powermode0_en = 0,
|
||||
pmu_pmu1_pd_byp = 1,
|
||||
pmu_pmu1_bus_byp = 2,
|
||||
pmu_pmu0_wkup_byp = 3,
|
||||
pmu_pmu0_pmic_byp = 4,
|
||||
pmu_pmu0_reset_byp = 5,
|
||||
pmu_pmu0_freq_switch_byp = 6,
|
||||
pmu_pmu0_osc_dis_byp = 7,
|
||||
pmu_pmu1_pwrgt = 8,
|
||||
pmu_pmu1_pwrgt_sft = 9,
|
||||
pmu_pmu1_mempwr_sft_gt = 10,
|
||||
pmu_pmu1_idle_en = 11,
|
||||
pmu_pmu1_idle_sft_en = 12,
|
||||
pmu_pmu1_noc_auto_en = 13,
|
||||
pmu_pmu1_off_io_en = 14,
|
||||
};
|
||||
|
||||
enum pmu1_pwr_con {
|
||||
pmu_powermode_en = 0,
|
||||
pmu_scu0_byp = 1,
|
||||
pmu_scu1_byp = 2,
|
||||
pmu_cci_byp = 3,
|
||||
pmu_bus_byp = 4,
|
||||
pmu_ddr_byp = 5,
|
||||
pmu_pwrgt_byp = 6,
|
||||
pmu_cru_byp = 7,
|
||||
pmu_qch_byp = 8,
|
||||
pmu_wfi_byp = 12,
|
||||
pmu_slp_cnt_en = 13,
|
||||
};
|
||||
|
||||
enum pmu_wakeup_int {
|
||||
pmu_wkup_cpu0_int = 0,
|
||||
pmu_wkup_cpu1_int = 1,
|
||||
pmu_wkup_cpu2_int = 2,
|
||||
pmu_wkup_cpu3_int = 3,
|
||||
pmu_wkup_cpu4_int = 4,
|
||||
pmu_wkup_cpu5_int = 5,
|
||||
pmu_wkup_cpu6_int = 6,
|
||||
pmu_wkup_cpu7_int = 7,
|
||||
pmu_wkup_gpio0_int = 8,
|
||||
pmu_wkup_sdmmc_int = 9,
|
||||
pmu_wkup_sdio_int = 10,
|
||||
pmu_wkup_usbdev_int = 11,
|
||||
pmu_wkup_uart_int = 12,
|
||||
pmu_wkup_mcu_int = 13,
|
||||
pmu_wkup_timer_int = 14,
|
||||
pmu_wkup_sys_int = 15,
|
||||
pmu_wkup_pwm_int = 16,
|
||||
pmu_wkup_tsadc_int = 17,
|
||||
pmu_wkup_hptimer_int = 18,
|
||||
pmu_wkup_saradc_int = 19,
|
||||
pmu_wkup_timeout = 20,
|
||||
};
|
||||
|
||||
/* PMU_DDR_PWR_CON */
|
||||
enum pmu_ddr_pwr_con {
|
||||
pmu_ddr_sref_c_en = 0,
|
||||
pmu_ddr_ioret_en = 1,
|
||||
pmu_ddr_ioret_exit_en = 2,
|
||||
pmu_ddr_rstiov_en = 3,
|
||||
pmu_ddr_rstiov_exit_en = 4,
|
||||
pmu_ddr_gating_c_en = 5,
|
||||
pmu_ddr_gating_p_en = 6,
|
||||
};
|
||||
|
||||
/* PMU_CRU_PWR_CON0 */
|
||||
enum pmu_cru_pwr_con0 {
|
||||
pmu_alive_32k_en = 0,
|
||||
pmu_osc_dis_en = 1,
|
||||
pmu_wakeup_rst_en = 2,
|
||||
pmu_input_clamp_en = 3,
|
||||
pmu_alive_osc_mode_en = 4,
|
||||
pmu_power_off_en = 5,
|
||||
pmu_pwm_switch_en = 6,
|
||||
pmu_pwm_gpio_ioe_en = 7,
|
||||
pmu_pwm_switch_io = 8,
|
||||
pmu_io_sleep_en = 9,
|
||||
};
|
||||
|
||||
/* PMU_CRU_PWR_CON1 */
|
||||
enum pmu_cru_pwr_con1 {
|
||||
pmu_bus_clksrc_gt_en = 0,
|
||||
pmu_vpu_clksrc_gt_en = 1,
|
||||
pmu_vo_clksrc_gt_en = 2,
|
||||
pmu_gpu_clksrc_gt_en = 3,
|
||||
pmu_rkenc_clksrc_gt_en = 4,
|
||||
pmu_rkvdec_clksrc_gt_en = 5,
|
||||
pmu_core_clksrc_gt_en = 6,
|
||||
pmu_ddr_clksrc_gt_en = 7,
|
||||
};
|
||||
|
||||
/* PMU_SCU_PWR_CON */
|
||||
enum pmu_scu_pwr_con {
|
||||
pmu_l2_flush_en = 0,
|
||||
pmu_l2_ilde_en = 1,
|
||||
pmu_scu_pd_en = 2,
|
||||
pmu_scu_pwroff_en = 3,
|
||||
pmu_clst_cpu_pd_en = 5,
|
||||
pmu_std_wfi_bypass = 8,
|
||||
pmu_std_wfil2_bypass = 9,
|
||||
pmu_scu_vol_gt_en = 10,
|
||||
};
|
||||
|
||||
/* PMU_PLLPD_CON */
|
||||
enum pmu_pllpd_con {
|
||||
pmu_d0apll_pd_en = 0,
|
||||
pmu_d0bpll_pd_en = 1,
|
||||
pmu_d1apll_pd_en = 2,
|
||||
pmu_d1bpll_pd_en = 3,
|
||||
pmu_bpll_pd_en = 4,
|
||||
pmu_lpll_pd_en = 5,
|
||||
pmu_spll_pd_en = 6,
|
||||
pmu_gpll_pd_en = 7,
|
||||
pmu_cpll_pd_en = 8,
|
||||
pmu_ppll_pd_en = 9,
|
||||
pmu_aupll_pd_en = 10,
|
||||
pmu_vpll_pd_en = 11,
|
||||
};
|
||||
|
||||
/* PMU_CLST_PWR_ST */
|
||||
enum pmu_clst_pwr_st {
|
||||
pmu_cpu0_wfi = 0,
|
||||
pmu_cpu1_wfi = 1,
|
||||
pmu_cpu2_wfi = 2,
|
||||
pmu_cpu3_wfi = 3,
|
||||
pmu_cpu4_wfi = 4,
|
||||
pmu_cpu5_wfi = 5,
|
||||
pmu_cpu6_wfi = 6,
|
||||
pmu_cpu7_wfi = 7,
|
||||
pmu_scu0_standbywfil2 = 8,
|
||||
pmu_scu1_standbywfil2 = 9,
|
||||
pmu_scu0_l2flushdone = 10,
|
||||
pmu_scu1_l2flushdone = 11,
|
||||
pmu_cpu0_pd_st = 16,
|
||||
pmu_cpu1_pd_st = 17,
|
||||
pmu_cpu2_pd_st = 18,
|
||||
pmu_cpu3_pd_st = 19,
|
||||
pmu_cpu4_pd_st = 20,
|
||||
pmu_cpu5_pd_st = 21,
|
||||
pmu_cpu6_pd_st = 22,
|
||||
pmu_cpu7_pd_st = 23,
|
||||
pmu_scu0_pd_st = 24,
|
||||
pmu_scu1_pd_st = 25,
|
||||
};
|
||||
|
||||
/* PMU_CLST_IDLE_CON */
|
||||
enum pmu_clst_idle_con {
|
||||
pmu_adb400s_idle_req = 0,
|
||||
pmu_clst_biu_idle_req = 1,
|
||||
pmu_clst_clk_gt_msk = 2,
|
||||
};
|
||||
|
||||
enum cores_pm_ctr_mode {
|
||||
core_pwr_pd = 0,
|
||||
core_pwr_wfi = 1,
|
||||
core_pwr_wfi_int = 2,
|
||||
core_pwr_wfi_reset = 3,
|
||||
};
|
||||
|
||||
/* PMU_CPUX_AUTO_PWR_CON */
|
||||
enum pmu_cpu_auto_pwr_con {
|
||||
pmu_cpu_pm_en = 0,
|
||||
pmu_cpu_pm_int_wakeup_en = 1,
|
||||
pmu_cpu_pm_dis_int = 2,
|
||||
pmu_cpu_pm_sft_wakeup_en = 3,
|
||||
};
|
||||
|
||||
enum qos_id {
|
||||
qos_decom = 0,
|
||||
qos_dmac0 = 1,
|
||||
qos_dmac1 = 2,
|
||||
qos_dmac2 = 3,
|
||||
qos_bus_mcu = 4,
|
||||
qos_can0 = 5,
|
||||
qos_can1 = 6,
|
||||
qos_cci_m0 = 7,
|
||||
qos_cci_m1 = 8,
|
||||
qos_cci_m2 = 9,
|
||||
qos_dap_lite = 10,
|
||||
qos_hdcp1 = 11,
|
||||
qos_ddr_mcu = 12,
|
||||
qos_fspi1 = 13,
|
||||
qos_gmac0 = 14,
|
||||
qos_gmac1 = 15,
|
||||
qos_sdio = 16,
|
||||
qos_sdmmc = 17,
|
||||
qos_flexbus = 18,
|
||||
qos_gpu = 19,
|
||||
qos_vepu1 = 20,
|
||||
qos_npu_mcu = 21,
|
||||
qos_npu_nsp0 = 22,
|
||||
qos_npu_nsp1 = 23,
|
||||
qos_npu_m0 = 24,
|
||||
qos_npu_m1 = 25,
|
||||
qos_npu_m0ro = 26,
|
||||
qos_npu_m1ro = 27,
|
||||
qos_emmc = 28,
|
||||
qos_fspi0 = 29,
|
||||
qos_mmu0 = 30,
|
||||
qos_mmu1 = 31,
|
||||
qos_pmu_mcu = 32,
|
||||
qos_rkvdec = 33,
|
||||
qos_crypto = 34,
|
||||
qos_mmu2 = 35,
|
||||
qos_ufshc = 36,
|
||||
qos_vepu0 = 37,
|
||||
qos_isp_mro = 38,
|
||||
qos_isp_mwo = 39,
|
||||
qos_vicap_m0 = 40,
|
||||
qos_vpss_mro = 41,
|
||||
qos_vpss_mwo = 42,
|
||||
qos_hdcp0 = 43,
|
||||
qos_vop_m0 = 44,
|
||||
qos_vop_m1ro = 45,
|
||||
qos_ebc = 46,
|
||||
qos_rga0 = 47,
|
||||
qos_rga1 = 48,
|
||||
qos_jpeg = 49,
|
||||
qos_vdpp = 50,
|
||||
qos_dma2ddr = 51,
|
||||
};
|
||||
|
||||
enum pmu_bus_id {
|
||||
pmu_bus_id_gpu = 0,
|
||||
pmu_bus_id_npu0 = 1,
|
||||
pmu_bus_id_npu1 = 2,
|
||||
pmu_bus_id_nputop = 3,
|
||||
pmu_bus_id_npusys = 4,
|
||||
pmu_bus_id_vpu = 5,
|
||||
pmu_bus_id_vdec = 6,
|
||||
pmu_bus_id_vepu0 = 7,
|
||||
pmu_bus_id_vepu1 = 8,
|
||||
pmu_bus_id_vi = 9,
|
||||
pmu_bus_id_usb = 10,
|
||||
pmu_bus_id_vo0 = 11,
|
||||
pmu_bus_id_vo1 = 12,
|
||||
pmu_bus_id_vop = 13,
|
||||
pmu_bus_id_vop_nocddrsch = 14,
|
||||
pmu_bus_id_php = 15,
|
||||
pmu_bus_id_audio = 16,
|
||||
pmu_bus_id_gmac = 17,
|
||||
pmu_bus_id_nvm = 18,
|
||||
pmu_bus_id_center_nocddrsch = 19,
|
||||
pmu_bus_id_center_nocmain = 20,
|
||||
pmu_bus_id_ddr = 21,
|
||||
pmu_bus_id_ddrsch0 = 22,
|
||||
pmu_bus_id_ddrsch1 = 23,
|
||||
pmu_bus_id_bus = 24,
|
||||
pmu_bus_id_secure = 25,
|
||||
pmu_bus_id_top = 26,
|
||||
pmu_bus_id_vo0vop_chn = 27,
|
||||
pmu_bus_id_cci = 28,
|
||||
pmu_bus_id_cci_nocddrsch = 29,
|
||||
pmu_bus_id_max,
|
||||
};
|
||||
|
||||
enum pmu_pd_id {
|
||||
pmu_pd_npu = 0,
|
||||
pmu_pd_bus = 1,
|
||||
pmu_pd_secure = 2,
|
||||
pmu_pd_center = 3,
|
||||
pmu_pd_ddr = 4,
|
||||
pmu_pd_cci = 5,
|
||||
pmu_pd_nvm = 6,
|
||||
pmu_pd_sd_gmac = 7,
|
||||
pmu_pd_audio = 8,
|
||||
pmu_pd_php = 9,
|
||||
pmu_pd_subphp = 10,
|
||||
pmu_pd_vop = 11,
|
||||
pmu_pd_vop_smart = 12,
|
||||
pmu_pd_vop_clst = 13,
|
||||
pmu_pd_vo1 = 14,
|
||||
pmu_pd_vo0 = 15,
|
||||
pmu_pd_usb = 16,
|
||||
pmu_pd_vi = 17,
|
||||
pmu_pd_vepu0 = 18,
|
||||
pmu_pd_vepu1 = 19,
|
||||
pmu_pd_vdec = 20,
|
||||
pmu_pd_vpu = 21,
|
||||
pmu_pd_nputop = 22,
|
||||
pmu_pd_npu0 = 23,
|
||||
pmu_pd_npu1 = 24,
|
||||
pmu_pd_gpu = 25,
|
||||
pmu_pd_id_max,
|
||||
};
|
||||
|
||||
enum pmu_vd_id {
|
||||
pmu_vd_npu = 0,
|
||||
pmu_vd_ddr = 1,
|
||||
pmu_vd_cci = 2,
|
||||
pmu_vd_gpu = 3,
|
||||
};
|
||||
|
||||
enum pmu_bus_state {
|
||||
pmu_bus_active = 0,
|
||||
pmu_bus_idle = 1,
|
||||
};
|
||||
|
||||
enum pmu_pd_state {
|
||||
pmu_pd_on = 0,
|
||||
pmu_pd_off = 1
|
||||
};
|
||||
|
||||
enum pmu_scu_fsm_st {
|
||||
pmu_scu_fsm_normal = 0,
|
||||
pmu_scu_fsm_cpu_pwr_down = 1,
|
||||
pmu_scu_fsm_l2_flush = 2,
|
||||
pmu_scu_fsm_l2_idle = 3,
|
||||
pmu_scu_fsm_clust_idle = 4,
|
||||
pmu_scu_fsm_scu_pwr_down = 5,
|
||||
pmu_scu_fsm_sleep = 6,
|
||||
pmu_scu_fsm_wkup = 7,
|
||||
pmu_scu_fsm_scu_pwr_up = 8,
|
||||
pmu_scu_fsm_clust_resume = 9,
|
||||
pmu_scu_fsm_cpu_pwr_up = 10,
|
||||
};
|
||||
|
||||
#define MAX_MEM_OS_REG_NUM 32
|
||||
#define MEM_OS_REG_BASE \
|
||||
(PMUSRAM_BASE + PMUSRAM_RSIZE - MAX_MEM_OS_REG_NUM * 4)
|
||||
|
||||
#define PSRAM_SP_TOP MEM_OS_REG_BASE
|
||||
|
||||
#define PD_CTR_LOOP 5000
|
||||
#define WFEI_CHECK_LOOP 5000
|
||||
#define BUS_IDLE_LOOP 1000
|
||||
#define NONBOOT_CPUS_OFF_LOOP 500000
|
||||
|
||||
#define REBOOT_FLAG 0x5242C300
|
||||
#define BOOT_BROM_DOWNLOAD 0xef08a53c
|
||||
|
||||
#define BOOTROM_SUSPEND_MAGIC 0x02468ace
|
||||
#define BOOTROM_RESUME_MAGIC 0x13579bdf
|
||||
#define WARM_BOOT_MAGIC 0x76543210
|
||||
#define VALID_GLB_RST_MSK 0xbfff
|
||||
|
||||
#define DEFAULT_BOOT_CPU 0
|
||||
|
||||
/*******************************************************
|
||||
* sleep mode define
|
||||
*******************************************************/
|
||||
#define SLP_ARMPD BIT(0)
|
||||
#define SLP_ARMOFF BIT(1)
|
||||
#define SLP_ARMOFF_DDRPD BIT(2)
|
||||
#define SLP_ARMOFF_LOGOFF BIT(3)
|
||||
#define SLP_ARMOFF_PMUOFF BIT(4)
|
||||
#define SLP_FROM_UBOOT BIT(5)
|
||||
|
||||
/* all plls except ddr's pll*/
|
||||
#define SLP_PMU_HW_PLLS_PD BIT(8)
|
||||
#define SLP_PMU_PMUALIVE_32K BIT(9)
|
||||
#define SLP_PMU_DIS_OSC BIT(10)
|
||||
|
||||
#define SLP_CLK_GT BIT(16)
|
||||
#define SLP_PMIC_LP BIT(17)
|
||||
|
||||
#define SLP_32K_EXT BIT(24)
|
||||
#define SLP_TIME_OUT_WKUP BIT(25)
|
||||
#define SLP_PMU_DBG BIT(26)
|
||||
#define SLP_ARCH_TIMER_RESET BIT(27)
|
||||
|
||||
#define PM_INVALID_GPIO 0xffff
|
||||
#define MAX_GPIO_POWER_CFG_CNT 10
|
||||
#define MAX_VIRTUAL_PWROFF_IRQ_CNT 20
|
||||
|
||||
enum {
|
||||
RK_PM_VIRT_PWROFF_EN = 0,
|
||||
RK_PM_VIRT_PWROFF_IRQ_CFG = 1,
|
||||
RK_PM_VIRT_PWROFF_MAX,
|
||||
};
|
||||
|
||||
/* sleep pin */
|
||||
#define RKPM_SLEEP_PIN0_EN BIT(0) /* GPIO0_A3 */
|
||||
#define RKPM_SLEEP_PIN1_EN BIT(1) /* GPIO0_A4 */
|
||||
#define RKPM_SLEEP_PIN2_EN BIT(2) /* GPIO0_A5 */
|
||||
|
||||
#define RKPM_SLEEP_PIN0_ACT_LOW BIT(0) /* GPIO0_A3 */
|
||||
#define RKPM_SLEEP_PIN1_ACT_LOW BIT(1) /* GPIO0_A4 */
|
||||
#define RKPM_SLEEP_PIN2_ACT_LOW BIT(2) /* GPIO0_A5 */
|
||||
|
||||
#define pmu_bus_idle_st(id) \
|
||||
(!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST) & BIT(id)))
|
||||
|
||||
#define pmu_bus_idle_ack(id) \
|
||||
(!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ACK) & BIT(id)))
|
||||
|
||||
static inline uint32_t read_mem_os_reg(uint32_t id)
|
||||
{
|
||||
assert((id) < MAX_MEM_OS_REG_NUM);
|
||||
|
||||
return mmio_read_32(MEM_OS_REG_BASE + 4 * (id));
|
||||
}
|
||||
|
||||
static inline void write_mem_os_reg(uint32_t id, uint32_t val)
|
||||
{
|
||||
assert((id) < MAX_MEM_OS_REG_NUM);
|
||||
|
||||
mmio_write_32(MEM_OS_REG_BASE + 4 * (id), val);
|
||||
}
|
||||
#endif /* __PMU_H__ */
|
||||
693
plat/rockchip/rk3576/drivers/secure/firewall.c
Normal file
693
plat/rockchip/rk3576/drivers/secure/firewall.c
Normal file
|
|
@ -0,0 +1,693 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <firewall.h>
|
||||
#include <soc.h>
|
||||
|
||||
enum {
|
||||
FW_NS_A_S_A = 0x0,
|
||||
FW_NS_A_S_NA = 0x1,
|
||||
FW_NS_NA_S_A = 0x2,
|
||||
FW_NS_NA_S_NA = 0x3,
|
||||
};
|
||||
|
||||
/* group type */
|
||||
enum {
|
||||
FW_GRP_TYPE_INV = 0,
|
||||
FW_GRP_TYPE_DDR_RGN = 1,
|
||||
FW_GRP_TYPE_SYSMEM_RGN = 2,
|
||||
FW_GRP_TYPE_CBUF_RGN = 3,
|
||||
FW_GRP_TYPE_SLV = 4,
|
||||
FW_GRP_TYPE_DM = 5,
|
||||
};
|
||||
|
||||
enum {
|
||||
FW_SLV_TYPE_INV = 0,
|
||||
FW_MST_TYPE_INV = 0,
|
||||
FW_SLV_TYPE_BUS = 1,
|
||||
FW_SLV_TYPE_TOP = 2,
|
||||
FW_SLV_TYPE_CENTER = 3,
|
||||
FW_SLV_TYPE_CCI = 4,
|
||||
FW_SLV_TYPE_PHP = 5,
|
||||
FW_SLV_TYPE_GPU = 6,
|
||||
FW_SLV_TYPE_NPU = 7,
|
||||
FW_SLV_TYPE_PMU = 8,
|
||||
FW_MST_TYPE_SYS = 9,
|
||||
FW_MST_TYPE_PMU = 10,
|
||||
};
|
||||
|
||||
#define FW_ID(type, id) \
|
||||
((((type) & 0xff) << 16) | ((id) & 0xffff))
|
||||
|
||||
#define FW_MST_ID(type, id) FW_ID(type, id)
|
||||
#define FW_SLV_ID(type, id) FW_ID(type, id)
|
||||
#define FW_GRP_ID(type, id) FW_ID(type, id)
|
||||
|
||||
/* group id */
|
||||
#define FW_GRP_ID_DDR_RGN(id) FW_GRP_ID(FW_GRP_TYPE_DDR_RGN, id)
|
||||
#define FW_GRP_ID_SYSMEM_RGN(id) FW_GRP_ID(FW_GRP_TYPE_SYSMEM_RGN, id)
|
||||
#define FW_GRP_ID_CBUF(id) FW_GRP_ID(FW_GRP_TYPE_CBUF_RGN, id)
|
||||
#define FW_GRP_ID_SLV(id) FW_GRP_ID(FW_GRP_TYPE_SLV, id)
|
||||
#define FW_GRP_ID_DM(id) FW_GRP_ID(FW_GRP_TYPE_DM, id)
|
||||
|
||||
#define FW_GRP_ID_SLV_CNT 8
|
||||
#define FW_GRP_ID_DM_CNT 8
|
||||
|
||||
#define FW_GET_ID(id) ((id) & 0xffff)
|
||||
#define FW_GET_TYPE(id) (((id) >> 16) & 0xff)
|
||||
|
||||
#define FW_INVLID_MST_ID FW_MST_ID(FW_MST_TYPE_INV, 0)
|
||||
#define FW_INVLID_SLV_ID FW_SLV_ID(FW_SLV_TYPE_INV, 0)
|
||||
|
||||
typedef struct {
|
||||
uint32_t domain[FW_SGRF_MST_DOMAIN_CON_CNT];
|
||||
uint32_t pmu_domain;
|
||||
uint32_t bus_slv_grp[FW_SGRF_BUS_SLV_CON_CNT];
|
||||
uint32_t top_slv_grp[FW_SGRF_TOP_SLV_CON_CNT];
|
||||
uint32_t center_slv_grp[FW_SGRF_CENTER_SLV_CON_CNT];
|
||||
uint32_t cci_slv_grp[FW_SGRF_CCI_SLV_CON_CNT];
|
||||
uint32_t php_slv_grp[FW_SGRF_PHP_SLV_CON_CNT];
|
||||
uint32_t gpu_slv_grp;
|
||||
uint32_t npu_slv_grp[FW_SGRF_NPU_SLV_CON_CNT];
|
||||
uint32_t pmu_slv_grp[FW_PMU_SGRF_SLV_CON_CNT];
|
||||
uint32_t ddr_rgn[FW_SGRF_DDR_RGN_CNT];
|
||||
uint32_t ddr_size;
|
||||
uint32_t ddr_con;
|
||||
uint32_t sysmem_rgn[FW_SGRF_SYSMEM_RGN_CNT];
|
||||
uint32_t sysmem_con;
|
||||
uint32_t cbuf_rgn[FW_SGRF_CBUF_RGN_CNT];
|
||||
uint32_t cbuf_con;
|
||||
uint32_t ddr_lookup[FW_SGRF_DDR_LOOKUP_CNT];
|
||||
uint32_t sysmem_lookup[FW_SGRF_SYSMEM_LOOKUP_CNT];
|
||||
uint32_t cbuf_lookup[FW_SGRF_CBUF_LOOKUP_CNT];
|
||||
uint32_t slv_lookup[FW_SGRF_SLV_LOOKUP_CNT];
|
||||
uint32_t pmu_slv_lookup[FW_PMU_SGRF_SLV_LOOKUP_CNT];
|
||||
} fw_config_t;
|
||||
|
||||
static fw_config_t fw_config_buf;
|
||||
|
||||
/****************************************************************************
|
||||
* Access rights between domains and groups are as follows:
|
||||
*
|
||||
* 00: NS access, S access
|
||||
* 01: NS access, S not access
|
||||
* 10: NS not access, S access
|
||||
* 11: NS not access, S not access
|
||||
* |---------------------------------------------------------|
|
||||
* | | d0 | d1 | d2 | d3 | d4 | d5 | d6 | d7 |
|
||||
* |---------------------------------------------------------|
|
||||
* | slave g0 | 00 | 00 | 11 | 11 | 11 | 11 | 11 | 00 |
|
||||
* |---------------------------------------------------------|
|
||||
* | slave g1 | 10 | 11 | 11 | 11 | 11 | 11 | 11 | 10 |
|
||||
* |---------------------------------------------------------|
|
||||
* | slave g2~7 | 11 | 11 | 11 | 11 | 11 | 11 | 11 | 11 |
|
||||
* |---------------------------------------------------------|
|
||||
* | ddr region 0~15 | 10 | 11 | 11 | 11 | 11 | 11 | 11 | 10 |
|
||||
* |---------------------------------------------------------|
|
||||
* | sram region 0~3 | 10 | 11 | 11 | 11 | 11 | 11 | 11 | 10 |
|
||||
* |---------------------------------------------------------|
|
||||
* | cbuf region 0~7 | 10 | 11 | 11 | 11 | 11 | 11 | 11 | 10 |
|
||||
* |---------------------------------------------------------|
|
||||
*
|
||||
* PS:
|
||||
* Domain 0/1/7 NS/S can access group 0.
|
||||
* Domain 0/1/7 NS and Domain1 NS/S can't access group 1, domain 0/7 S can access.
|
||||
* Other domains NS/S can't access all groups.
|
||||
*
|
||||
* Domain 0/7 NS can't access ddr/sram/cbuf region and Domain 0/7 S can access.
|
||||
* Other domains NS/S can't access ddr/sram/cbuf region.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Masters in dm1 */
|
||||
static const int dm1_mst[] = {
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 1), /* keylad_apbm */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 2), /* dft2apbm */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 11), /* dma2ddr */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 12), /* dmac0 */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 13), /* dmac1 */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 14), /* dmac2 */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 19), /* gpu */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 31), /* vop_m0 */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 32), /* vop_m1 */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 36), /* bus_mcu */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 38), /* npu_mcu */
|
||||
FW_MST_ID(FW_MST_TYPE_SYS, 56), /* dap_lite */
|
||||
|
||||
FW_INVLID_MST_ID
|
||||
};
|
||||
|
||||
/* Slaves in group1 */
|
||||
static const int sec_slv[] = {
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 28), /* crypto_s */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 29), /* keyladder_s */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 30), /* rkrng_s */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 33), /* jtag_lock */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 34), /* otp_s */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 35), /* otpmsk */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 37), /* scru_s */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 38), /* sys_sgrf */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 39), /* bootrom */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 41), /* wdts */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 44), /* sevice_secure */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 61), /* timers0_ch0~5 */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 62),
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 63),
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 64),
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 65),
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 66),
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 67), /* timers1_ch0~5 */
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 68),
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 69),
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 70),
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 71),
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 72),
|
||||
FW_SLV_ID(FW_SLV_TYPE_TOP, 73), /* sys_fw */
|
||||
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 3), /* ddr grf */
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 4), /* ddr ctl0 */
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 5), /* ddr ctl1 */
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 6), /* ddr phy0 */
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 7), /* ddr0 cru */
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 8), /* ddr phy1 */
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 9), /* ddr1 cru */
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 15), /* ddr wdt */
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 19), /* service ddr */
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 58), /* ddr timer ch0 */
|
||||
FW_SLV_ID(FW_SLV_TYPE_CENTER, 59), /* ddr timer ch1 */
|
||||
|
||||
FW_SLV_ID(FW_SLV_TYPE_PMU, 1), /* pmu mem */
|
||||
FW_SLV_ID(FW_SLV_TYPE_PMU, 15), /* pmu1_scru */
|
||||
FW_SLV_ID(FW_SLV_TYPE_PMU, 30), /* osc chk */
|
||||
FW_SLV_ID(FW_SLV_TYPE_PMU, 31), /* pmu0_sgrf */
|
||||
FW_SLV_ID(FW_SLV_TYPE_PMU, 32), /* pmu1_sgrf */
|
||||
FW_SLV_ID(FW_SLV_TYPE_PMU, 34), /* scramble key */
|
||||
FW_SLV_ID(FW_SLV_TYPE_PMU, 36), /* pmu remap */
|
||||
FW_SLV_ID(FW_SLV_TYPE_PMU, 43), /* pmu fw */
|
||||
|
||||
FW_INVLID_SLV_ID
|
||||
};
|
||||
|
||||
static void fw_buf_sys_mst_dm_cfg(int mst_id, uint32_t dm_id)
|
||||
{
|
||||
int sft = (mst_id & 0x7) << 2;
|
||||
|
||||
fw_config_buf.domain[mst_id >> 3] &= ~(0xf << sft);
|
||||
fw_config_buf.domain[mst_id >> 3] |= (dm_id & 0xf) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_pmu_mst_dm_cfg(int mst_id, uint32_t dm_id)
|
||||
{
|
||||
int sft = (mst_id & 0x7) << 2;
|
||||
|
||||
fw_config_buf.pmu_domain &= ~(0xf << sft);
|
||||
fw_config_buf.pmu_domain |= (dm_id & 0xf) << sft;
|
||||
}
|
||||
|
||||
void fw_buf_mst_dm_cfg(int mst_id, uint32_t dm_id)
|
||||
{
|
||||
int type = FW_GET_TYPE(mst_id);
|
||||
|
||||
mst_id = FW_GET_ID(mst_id);
|
||||
|
||||
switch (type) {
|
||||
case FW_MST_TYPE_SYS:
|
||||
fw_buf_sys_mst_dm_cfg(mst_id, dm_id);
|
||||
break;
|
||||
case FW_MST_TYPE_PMU:
|
||||
fw_buf_pmu_mst_dm_cfg(mst_id, dm_id);
|
||||
break;
|
||||
|
||||
default:
|
||||
ERROR("%s: unknown FW_DOMAIN_TYPE (0x%x)\n", __func__, type);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void fw_buf_ddr_lookup_cfg(int rgn_id, int dm_id, uint32_t priv)
|
||||
{
|
||||
int sft = (dm_id << 1) + (rgn_id & 0x1) * 16;
|
||||
|
||||
fw_config_buf.ddr_lookup[rgn_id >> 1] &= ~(0x3 << sft);
|
||||
fw_config_buf.ddr_lookup[rgn_id >> 1] |= (priv & 0x3) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_sysmem_lookup_cfg(int rgn_id, int dm_id, uint32_t priv)
|
||||
{
|
||||
int sft = (dm_id << 1) + (rgn_id & 0x1) * 16;
|
||||
|
||||
fw_config_buf.sysmem_lookup[rgn_id >> 1] &= ~(0x3 << sft);
|
||||
fw_config_buf.sysmem_lookup[rgn_id >> 1] |= (priv & 0x3) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_cbuf_lookup_cfg(int rgn_id, int dm_id, uint32_t priv)
|
||||
{
|
||||
int sft = (dm_id << 1) + (rgn_id & 0x1) * 16;
|
||||
|
||||
fw_config_buf.cbuf_lookup[rgn_id >> 1] &= ~(0x3 << sft);
|
||||
fw_config_buf.cbuf_lookup[rgn_id >> 1] |= (priv & 0x3) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_slv_lookup_cfg(int grp_id, int dm_id, uint32_t priv)
|
||||
{
|
||||
int sft = (dm_id << 1) + (grp_id & 0x1) * 16;
|
||||
|
||||
fw_config_buf.slv_lookup[grp_id >> 1] &= ~(0x3 << sft);
|
||||
fw_config_buf.slv_lookup[grp_id >> 1] |= (priv & 0x3) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_pmu_slv_lookup_cfg(int grp_id, int dm_id, uint32_t priv)
|
||||
{
|
||||
int sft = (dm_id << 1) + (grp_id & 0x1) * 16;
|
||||
|
||||
fw_config_buf.pmu_slv_lookup[grp_id >> 1] &= ~(0x3 << sft);
|
||||
fw_config_buf.pmu_slv_lookup[grp_id >> 1] |= (priv & 0x3) << sft;
|
||||
}
|
||||
|
||||
void fw_buf_grp_lookup_cfg(int grp_id, int dm_id, uint32_t priv)
|
||||
{
|
||||
uint32_t type = FW_GET_TYPE(grp_id);
|
||||
|
||||
grp_id = FW_GET_ID(grp_id);
|
||||
|
||||
switch (type) {
|
||||
case FW_GRP_TYPE_DDR_RGN:
|
||||
fw_buf_ddr_lookup_cfg(grp_id, dm_id, priv);
|
||||
break;
|
||||
case FW_GRP_TYPE_SYSMEM_RGN:
|
||||
fw_buf_sysmem_lookup_cfg(grp_id, dm_id, priv);
|
||||
break;
|
||||
case FW_GRP_TYPE_CBUF_RGN:
|
||||
fw_buf_cbuf_lookup_cfg(grp_id, dm_id, priv);
|
||||
break;
|
||||
case FW_GRP_TYPE_SLV:
|
||||
fw_buf_slv_lookup_cfg(grp_id, dm_id, priv);
|
||||
fw_buf_pmu_slv_lookup_cfg(grp_id, dm_id, priv);
|
||||
break;
|
||||
|
||||
default:
|
||||
ERROR("%s: unknown FW_LOOKUP_TYPE (0x%x)\n", __func__, type);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void fw_buf_bus_slv_grp_cfg(int slv_id, int grp_id)
|
||||
{
|
||||
int sft = slv_id % 5 << 2;
|
||||
|
||||
fw_config_buf.bus_slv_grp[slv_id / 5] &= ~(0xf << sft);
|
||||
fw_config_buf.bus_slv_grp[slv_id / 5] |= (grp_id & 0xf) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_top_slv_grp_cfg(int slv_id, int grp_id)
|
||||
{
|
||||
int sft = slv_id % 5 << 2;
|
||||
|
||||
fw_config_buf.top_slv_grp[slv_id / 5] &= ~(0xf << sft);
|
||||
fw_config_buf.top_slv_grp[slv_id / 5] |= (grp_id & 0xf) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_center_slv_grp_cfg(int slv_id, int grp_id)
|
||||
{
|
||||
int sft = slv_id % 5 << 2;
|
||||
|
||||
fw_config_buf.center_slv_grp[slv_id / 5] &= ~(0xf << sft);
|
||||
fw_config_buf.center_slv_grp[slv_id / 5] |= (grp_id & 0xf) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_cci_slv_grp_cfg(int slv_id, int grp_id)
|
||||
{
|
||||
int sft = slv_id % 5 << 2;
|
||||
|
||||
fw_config_buf.cci_slv_grp[slv_id / 5] &= ~(0xf << sft);
|
||||
fw_config_buf.cci_slv_grp[slv_id / 5] |= (grp_id & 0xf) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_php_slv_grp_cfg(int slv_id, int grp_id)
|
||||
{
|
||||
int sft = slv_id % 5 << 2;
|
||||
|
||||
fw_config_buf.php_slv_grp[slv_id / 5] &= ~(0xf << sft);
|
||||
fw_config_buf.php_slv_grp[slv_id / 5] |= (grp_id & 0xf) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_gpu_slv_grp_cfg(int slv_id, int grp_id)
|
||||
{
|
||||
int sft = slv_id % 5 << 2;
|
||||
|
||||
fw_config_buf.gpu_slv_grp &= ~(0xf << sft);
|
||||
fw_config_buf.gpu_slv_grp |= (grp_id & 0xf) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_npu_slv_grp_cfg(int slv_id, int grp_id)
|
||||
{
|
||||
int sft = slv_id % 5 << 2;
|
||||
|
||||
fw_config_buf.npu_slv_grp[slv_id / 5] &= ~(0xf << sft);
|
||||
fw_config_buf.npu_slv_grp[slv_id / 5] |= (grp_id & 0xf) << sft;
|
||||
}
|
||||
|
||||
static void fw_buf_pmu_slv_grp_cfg(int slv_id, int grp_id)
|
||||
{
|
||||
int sft = slv_id % 5 << 2;
|
||||
|
||||
fw_config_buf.pmu_slv_grp[slv_id / 5] &= ~(0xf << sft);
|
||||
fw_config_buf.pmu_slv_grp[slv_id / 5] |= (grp_id & 0xf) << sft;
|
||||
}
|
||||
|
||||
void fw_buf_slv_grp_cfg(int slv_id, int grp_id)
|
||||
{
|
||||
int type = FW_GET_TYPE(slv_id);
|
||||
|
||||
slv_id = FW_GET_ID(slv_id);
|
||||
grp_id = FW_GET_ID(grp_id);
|
||||
|
||||
switch (type) {
|
||||
case FW_SLV_TYPE_BUS:
|
||||
fw_buf_bus_slv_grp_cfg(slv_id, grp_id);
|
||||
break;
|
||||
case FW_SLV_TYPE_TOP:
|
||||
fw_buf_top_slv_grp_cfg(slv_id, grp_id);
|
||||
break;
|
||||
case FW_SLV_TYPE_CENTER:
|
||||
fw_buf_center_slv_grp_cfg(slv_id, grp_id);
|
||||
break;
|
||||
case FW_SLV_TYPE_CCI:
|
||||
fw_buf_cci_slv_grp_cfg(slv_id, grp_id);
|
||||
break;
|
||||
case FW_SLV_TYPE_PHP:
|
||||
fw_buf_php_slv_grp_cfg(slv_id, grp_id);
|
||||
break;
|
||||
case FW_SLV_TYPE_GPU:
|
||||
fw_buf_gpu_slv_grp_cfg(slv_id, grp_id);
|
||||
break;
|
||||
case FW_SLV_TYPE_NPU:
|
||||
fw_buf_npu_slv_grp_cfg(slv_id, grp_id);
|
||||
break;
|
||||
case FW_SLV_TYPE_PMU:
|
||||
fw_buf_pmu_slv_grp_cfg(slv_id, grp_id);
|
||||
break;
|
||||
|
||||
default:
|
||||
ERROR("%s: unknown FW_SLV_TYPE (0x%x)\n", __func__, type);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void fw_buf_add_msts(const int *mst_ids, int dm_id)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; FW_GET_TYPE(mst_ids[i]) != FW_INVLID_SLV_ID; i++)
|
||||
fw_buf_mst_dm_cfg(mst_ids[i], dm_id);
|
||||
}
|
||||
|
||||
void fw_buf_add_slvs(const int *slv_ids, int grp_id)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; FW_GET_TYPE(slv_ids[i]) != FW_INVLID_SLV_ID; i++)
|
||||
fw_buf_slv_grp_cfg(slv_ids[i], grp_id);
|
||||
}
|
||||
|
||||
/* unit: Mb */
|
||||
void fw_buf_ddr_size_cfg(uint64_t base_mb, uint64_t top_mb, int id)
|
||||
{
|
||||
fw_config_buf.ddr_size = RG_MAP_SECURE(top_mb, base_mb);
|
||||
fw_config_buf.ddr_con |= BIT(16);
|
||||
}
|
||||
|
||||
/* unit: Mb */
|
||||
void fw_buf_ddr_rgn_cfg(uint64_t base_mb, uint64_t top_mb, int rgn_id)
|
||||
{
|
||||
fw_config_buf.ddr_rgn[rgn_id] = RG_MAP_SECURE(top_mb, base_mb);
|
||||
fw_config_buf.ddr_con |= BIT(rgn_id);
|
||||
}
|
||||
|
||||
/* Unit: kb */
|
||||
void fw_buf_sysmem_rgn_cfg(uint64_t base_kb, uint64_t top_kb, int rgn_id)
|
||||
{
|
||||
fw_config_buf.sysmem_rgn[rgn_id] = RG_MAP_SRAM_SECURE(top_kb, base_kb);
|
||||
fw_config_buf.sysmem_con |= BIT(rgn_id);
|
||||
}
|
||||
|
||||
static void fw_domain_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* select to domain0 by default */
|
||||
for (i = 0; i < FW_SGRF_MST_DOMAIN_CON_CNT; i++)
|
||||
fw_config_buf.domain[i] = 0x0;
|
||||
|
||||
/* select to domain0 by default */
|
||||
fw_config_buf.pmu_domain = 0x0;
|
||||
}
|
||||
|
||||
static void fw_slv_grp_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* select to group0 by default */
|
||||
for (i = 0; i < FW_SGRF_BUS_SLV_CON_CNT; i++)
|
||||
fw_config_buf.bus_slv_grp[i] = 0x0;
|
||||
|
||||
for (i = 0; i < FW_SGRF_TOP_SLV_CON_CNT; i++)
|
||||
fw_config_buf.top_slv_grp[i] = 0x0;
|
||||
|
||||
for (i = 0; i < FW_SGRF_CENTER_SLV_CON_CNT; i++)
|
||||
fw_config_buf.center_slv_grp[i] = 0x0;
|
||||
|
||||
for (i = 0; i < FW_SGRF_CCI_SLV_CON_CNT; i++)
|
||||
fw_config_buf.cci_slv_grp[i] = 0x0;
|
||||
|
||||
for (i = 0; i < FW_SGRF_PHP_SLV_CON_CNT; i++)
|
||||
fw_config_buf.php_slv_grp[i] = 0x0;
|
||||
|
||||
fw_config_buf.gpu_slv_grp = 0x0;
|
||||
|
||||
for (i = 0; i < FW_SGRF_NPU_SLV_CON_CNT; i++)
|
||||
fw_config_buf.npu_slv_grp[i] = 0x0;
|
||||
}
|
||||
|
||||
static void fw_region_init(void)
|
||||
{
|
||||
/* Use FW_DDR_RGN0_REG to config 1024~1025M space to secure */
|
||||
fw_buf_ddr_rgn_cfg(1024, 1025, 0);
|
||||
|
||||
/* Use FW_SYSMEM_RGN0_REG to config 0~32k space to secure */
|
||||
fw_buf_sysmem_rgn_cfg(0, 32, 0);
|
||||
}
|
||||
|
||||
static void fw_lookup_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Domain 0/7 NS can't access ddr/sram/cbuf region and Domain 0/7 S can access.
|
||||
* Other domains NS/S can't access ddr/sram/cbuf region.
|
||||
*/
|
||||
for (i = 0; i < FW_SGRF_DDR_LOOKUP_CNT; i++)
|
||||
fw_config_buf.ddr_lookup[i] = 0xbffebffe;
|
||||
|
||||
for (i = 0; i < FW_SGRF_SYSMEM_LOOKUP_CNT; i++)
|
||||
fw_config_buf.sysmem_lookup[i] = 0xbffebffe;
|
||||
|
||||
for (i = 0; i < FW_SGRF_CBUF_LOOKUP_CNT; i++)
|
||||
fw_config_buf.cbuf_lookup[i] = 0xbffebffe;
|
||||
|
||||
/*
|
||||
* Domain 0/1/7 NS/S can access group 0.
|
||||
* Domain 0/1/7 NS and Domain1 NS/S can't access group 1, domain 0/7 S can access.
|
||||
* Other domains NS/S can't access all groups.
|
||||
*/
|
||||
fw_config_buf.slv_lookup[0] = 0xbffe3ff0;
|
||||
fw_config_buf.slv_lookup[1] = 0xffffffff;
|
||||
fw_config_buf.slv_lookup[2] = 0xffffffff;
|
||||
fw_config_buf.slv_lookup[3] = 0xffffffff;
|
||||
|
||||
/*
|
||||
* Domain 0/1/7 NS/S can access group 0.
|
||||
* Domain 0/1/7 NS and Domain1 NS/S can't access group 1, domain 0/7 S can access.
|
||||
* Other domains NS/S can't access all groups.
|
||||
*/
|
||||
fw_config_buf.pmu_slv_lookup[0] = 0xbffe3ff0;
|
||||
fw_config_buf.pmu_slv_lookup[1] = 0xffffffff;
|
||||
fw_config_buf.pmu_slv_lookup[2] = 0xffffffff;
|
||||
fw_config_buf.pmu_slv_lookup[3] = 0xffffffff;
|
||||
}
|
||||
|
||||
static void fw_config_buf_flush(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* domain */
|
||||
for (i = 0; i < FW_SGRF_MST_DOMAIN_CON_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_MST_DOMAIN_CON(i),
|
||||
fw_config_buf.domain[i]);
|
||||
|
||||
mmio_write_32(PMU1SGRF_FW_BASE + FW_PMU_SGRF_DOMAIN_CON,
|
||||
fw_config_buf.pmu_domain);
|
||||
|
||||
/* slave group */
|
||||
for (i = 0; i < FW_SGRF_BUS_SLV_CON_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_BUS_SLV_CON(i),
|
||||
fw_config_buf.bus_slv_grp[i]);
|
||||
|
||||
for (i = 0; i < FW_SGRF_TOP_SLV_CON_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_TOP_SLV_CON(i),
|
||||
fw_config_buf.top_slv_grp[i]);
|
||||
|
||||
for (i = 0; i < FW_SGRF_CENTER_SLV_CON_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_CENTER_SLV_CON(i),
|
||||
fw_config_buf.center_slv_grp[i]);
|
||||
|
||||
for (i = 0; i < FW_SGRF_CCI_SLV_CON_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_CCI_SLV_CON(i),
|
||||
fw_config_buf.cci_slv_grp[i]);
|
||||
|
||||
for (i = 0; i < FW_SGRF_PHP_SLV_CON_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_PHP_SLV_CON(i),
|
||||
fw_config_buf.php_slv_grp[i]);
|
||||
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_GPU_SLV_CON,
|
||||
fw_config_buf.gpu_slv_grp);
|
||||
|
||||
for (i = 0; i < FW_SGRF_NPU_SLV_CON_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_NPU_SLV_CON(i),
|
||||
fw_config_buf.npu_slv_grp[i]);
|
||||
|
||||
for (i = 0; i < FW_PMU_SGRF_SLV_CON_CNT; i++)
|
||||
mmio_write_32(PMU1SGRF_FW_BASE + FW_PMU_SGRF_SLV_CON(i),
|
||||
fw_config_buf.pmu_slv_grp[i]);
|
||||
|
||||
/* region */
|
||||
for (i = 0; i < FW_SGRF_DDR_RGN_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_DDR_RGN(i),
|
||||
fw_config_buf.ddr_rgn[i]);
|
||||
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_DDR_SIZE, fw_config_buf.ddr_size);
|
||||
|
||||
for (i = 0; i < FW_SGRF_SYSMEM_RGN_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_SYSMEM_RGN(i),
|
||||
fw_config_buf.sysmem_rgn[i]);
|
||||
|
||||
for (i = 0; i < FW_SGRF_CBUF_RGN_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_CBUF_RGN(i),
|
||||
fw_config_buf.cbuf_rgn[i]);
|
||||
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_DDR_CON, fw_config_buf.ddr_con);
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_SYSMEM_CON, fw_config_buf.sysmem_con);
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_CBUF_CON, fw_config_buf.cbuf_con);
|
||||
|
||||
dsb();
|
||||
isb();
|
||||
|
||||
/* lookup */
|
||||
for (i = 0; i < FW_SGRF_DDR_LOOKUP_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_DDR_LOOKUP(i),
|
||||
fw_config_buf.ddr_lookup[i]);
|
||||
|
||||
for (i = 0; i < FW_SGRF_SYSMEM_LOOKUP_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_SYSMEM_LOOKUP(i),
|
||||
fw_config_buf.sysmem_lookup[i]);
|
||||
|
||||
for (i = 0; i < FW_SGRF_CBUF_LOOKUP_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_CBUF_LOOKUP(i),
|
||||
fw_config_buf.cbuf_lookup[i]);
|
||||
|
||||
for (i = 0; i < FW_SGRF_SLV_LOOKUP_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_SLV_LOOKUP(i),
|
||||
fw_config_buf.slv_lookup[i]);
|
||||
|
||||
for (i = 0; i < FW_PMU_SGRF_SLV_LOOKUP_CNT; i++)
|
||||
mmio_write_32(PMU1SGRF_FW_BASE + FW_PMU_SGRF_SLV_LOOKUP(i),
|
||||
fw_config_buf.pmu_slv_lookup[i]);
|
||||
|
||||
dsb();
|
||||
isb();
|
||||
}
|
||||
|
||||
static __pmusramfunc void pmusram_udelay(uint32_t us)
|
||||
{
|
||||
uint64_t orig;
|
||||
uint64_t to_wait;
|
||||
|
||||
orig = read_cntpct_el0();
|
||||
to_wait = read_cntfrq_el0() * us / 1000000;
|
||||
|
||||
while (read_cntpct_el0() - orig <= to_wait)
|
||||
;
|
||||
}
|
||||
|
||||
__pmusramfunc void pmusram_fw_update_msk(uint32_t msk)
|
||||
{
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON0,
|
||||
BITS_WITH_WMASK(0, 0x3ff, 0));
|
||||
dsb();
|
||||
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON0,
|
||||
BITS_WITH_WMASK(msk, msk, 0));
|
||||
dsb();
|
||||
isb();
|
||||
pmusram_udelay(20);
|
||||
dsb();
|
||||
isb();
|
||||
}
|
||||
|
||||
__pmusramfunc void pmusram_all_fw_bypass(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* disable regions */
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_DDR_CON, 0);
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_SYSMEM_CON, 0);
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_CBUF_CON, 0);
|
||||
|
||||
for (i = 0; i < FW_SGRF_DDR_LOOKUP_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_DDR_LOOKUP(i), 0x0);
|
||||
|
||||
for (i = 0; i < FW_SGRF_SYSMEM_LOOKUP_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_SYSMEM_LOOKUP(i), 0x0);
|
||||
|
||||
for (i = 0; i < FW_SGRF_CBUF_LOOKUP_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_CBUF_LOOKUP(i), 0x0);
|
||||
|
||||
for (i = 0; i < FW_SGRF_SLV_LOOKUP_CNT; i++)
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_SLV_LOOKUP(i), 0x0);
|
||||
|
||||
for (i = 0; i < FW_PMU_SGRF_SLV_LOOKUP_CNT; i++)
|
||||
mmio_write_32(PMU1SGRF_FW_BASE + FW_PMU_SGRF_SLV_LOOKUP(i), 0x0);
|
||||
|
||||
dsb();
|
||||
|
||||
pmusram_fw_update_msk(0x3ff);
|
||||
}
|
||||
|
||||
void fw_init(void)
|
||||
{
|
||||
/* Enable all fw auto-update */
|
||||
mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON1, 0x03ff03ff);
|
||||
|
||||
pmusram_all_fw_bypass();
|
||||
|
||||
fw_domain_init();
|
||||
fw_slv_grp_init();
|
||||
fw_region_init();
|
||||
|
||||
fw_buf_add_slvs(sec_slv, 1);
|
||||
fw_buf_add_msts(dm1_mst, 1);
|
||||
|
||||
fw_lookup_init();
|
||||
|
||||
fw_config_buf_flush();
|
||||
pmusram_fw_update_msk(0x3ff);
|
||||
}
|
||||
499
plat/rockchip/rk3576/drivers/secure/firewall.h
Normal file
499
plat/rockchip/rk3576/drivers/secure/firewall.h
Normal file
|
|
@ -0,0 +1,499 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __FIREWALL_H__
|
||||
#define __FIREWALL_H__
|
||||
|
||||
#include <plat_private.h>
|
||||
|
||||
/* FW SGRF */
|
||||
#define FW_SGRF_MST_DOMAIN_CON(i) ((i) * 4)
|
||||
#define FW_SGRF_MST_DOMAIN_CON_CNT 8
|
||||
#define FW_SGRF_DDR_RGN(i) (0x0100 + (i) * 4)
|
||||
#define FW_SGRF_DDR_RGN_CNT 16
|
||||
#define FW_SGRF_DDR_LOOKUP(i) (0x0140 + (i) * 0x4)
|
||||
#define FW_SGRF_DDR_LOOKUP_CNT 8
|
||||
#define FW_SGRF_DDR_SIZE 0x0160
|
||||
#define FW_SGRF_DDR_CON 0x0168
|
||||
#define FW_SGRF_SYSMEM_RGN(i) (0x0200 + (i) * 4)
|
||||
#define FW_SGRF_SYSMEM_RGN_CNT 4
|
||||
#define FW_SGRF_SYSMEM_LOOKUP(i) (0x0210 + (i) * 4)
|
||||
#define FW_SGRF_SYSMEM_LOOKUP_CNT 2
|
||||
#define FW_SGRF_SYSMEM_CON 0x0218
|
||||
#define FW_SGRF_CBUF_RGN(i) (0x0300 + (i) * 4)
|
||||
#define FW_SGRF_CBUF_RGN_CNT 8
|
||||
#define FW_SGRF_CBUF_LOOKUP(i) (0x0320 + (i) * 4)
|
||||
#define FW_SGRF_CBUF_LOOKUP_CNT 4
|
||||
#define FW_SGRF_CBUF_CON 0x0330
|
||||
#define FW_SGRF_SLV_LOOKUP(i) (0x0400 + (i) * 4)
|
||||
#define FW_SGRF_SLV_LOOKUP_CNT 4
|
||||
#define FW_SGRF_BUS_SLV_CON(i) (0x0500 + (i) * 4)
|
||||
#define FW_SGRF_BUS_SLV_CON_CNT 25
|
||||
#define FW_SGRF_BUS_SLV_STAT 0x0580
|
||||
#define FW_SGRF_TOP_SLV_CON(i) (0x0600 + (i) * 4)
|
||||
#define FW_SGRF_TOP_SLV_CON_CNT 16
|
||||
#define FW_SGRF_TOP_SLV_STAT 0x0680
|
||||
#define FW_SGRF_CENTER_SLV_CON(i) (0x0700 + (i) * 4)
|
||||
#define FW_SGRF_CENTER_SLV_CON_CNT 13
|
||||
#define FW_SGRF_CCI_SLV_CON(i) (0x0800 + (i) * 4)
|
||||
#define FW_SGRF_CCI_SLV_CON_CNT 3
|
||||
#define FW_SGRF_PHP_SLV_CON(i) (0x0900 + (i) * 4)
|
||||
#define FW_SGRF_PHP_SLV_CON_CNT 4
|
||||
#define FW_SGRF_PHP_SLV_STAT 0x0940
|
||||
#define FW_SGRF_GPU_SLV_CON 0x0980
|
||||
#define FW_SGRF_NPU_SLV_CON(i) (0x09a0 + (i) * 4)
|
||||
#define FW_SGRF_NPU_SLV_CON_CNT 2
|
||||
#define FW_SGRF_STATCLR_CON0 0x0a00
|
||||
#define FW_SGRF_KEYUPD_CON0 0x0a80
|
||||
#define FW_SGRF_KEYUPD_CON1 0x0a84
|
||||
#define FW_SGRF_KEYUPD_STAT 0x0ab0
|
||||
|
||||
/* FW PMUSGRF */
|
||||
#define FW_PMU_SGRF_SLV_CON(i) ((i) * 4)
|
||||
#define FW_PMU_SGRF_SLV_CON_CNT 9
|
||||
#define FW_PMU_SGRF_SLV_LOOKUP(i) (0x0080 + (i) * 0x4)
|
||||
#define FW_PMU_SGRF_SLV_LOOKUP_CNT 4
|
||||
#define FW_PMU_SGRF_DOMAIN_CON 0x00a0
|
||||
#define FW_PMU_SGRF_SLV_STAT 0x00c0
|
||||
|
||||
/* master id */
|
||||
#define FW_MST_ID_USB0 FW_MST_ID(FW_MST_TYPE_SYS, 0)
|
||||
#define FW_MST_ID_KEYLAD_APB FW_MST_ID(FW_MST_TYPE_SYS, 1)
|
||||
#define FW_MST_ID_DFT2APB FW_MST_ID(FW_MST_TYPE_SYS, 2)
|
||||
#define FW_MST_ID_PCIE0 FW_MST_ID(FW_MST_TYPE_SYS, 3)
|
||||
#define FW_MST_ID_PCIE1 FW_MST_ID(FW_MST_TYPE_SYS, 4)
|
||||
#define FW_MST_ID_SATA0 FW_MST_ID(FW_MST_TYPE_SYS, 6)
|
||||
#define FW_MST_ID_SATA1 FW_MST_ID(FW_MST_TYPE_SYS, 7)
|
||||
#define FW_MST_ID_CRYPTO FW_MST_ID(FW_MST_TYPE_SYS, 8)
|
||||
#define FW_MST_ID_FLEXBUS FW_MST_ID(FW_MST_TYPE_SYS, 9)
|
||||
#define FW_MST_ID_DECOM FW_MST_ID(FW_MST_TYPE_SYS, 10)
|
||||
#define FW_MST_ID_DMA2DDR FW_MST_ID(FW_MST_TYPE_SYS, 11)
|
||||
#define FW_MST_ID_DMAC0 FW_MST_ID(FW_MST_TYPE_SYS, 12)
|
||||
#define FW_MST_ID_DMAC1 FW_MST_ID(FW_MST_TYPE_SYS, 13)
|
||||
#define FW_MST_ID_DMAC2 FW_MST_ID(FW_MST_TYPE_SYS, 14)
|
||||
#define FW_MST_ID_EBC FW_MST_ID(FW_MST_TYPE_SYS, 15)
|
||||
#define FW_MST_ID_EMMC FW_MST_ID(FW_MST_TYPE_SYS, 16)
|
||||
#define FW_MST_ID_GMAC0 FW_MST_ID(FW_MST_TYPE_SYS, 17)
|
||||
#define FW_MST_ID_GMAC1 FW_MST_ID(FW_MST_TYPE_SYS, 18)
|
||||
#define FW_MST_ID_GPU FW_MST_ID(FW_MST_TYPE_SYS, 19)
|
||||
#define FW_MST_ID_HDCP0 FW_MST_ID(FW_MST_TYPE_SYS, 20)
|
||||
#define FW_MST_ID_HDCP1 FW_MST_ID(FW_MST_TYPE_SYS, 21)
|
||||
#define FW_MST_ID_ISP FW_MST_ID(FW_MST_TYPE_SYS, 22)
|
||||
#define FW_MST_ID_RGA0 FW_MST_ID(FW_MST_TYPE_SYS, 23)
|
||||
#define FW_MST_ID_RGA1 FW_MST_ID(FW_MST_TYPE_SYS, 24)
|
||||
#define FW_MST_ID_JPEG FW_MST_ID(FW_MST_TYPE_SYS, 25)
|
||||
#define FW_MST_ID_RKVDEC FW_MST_ID(FW_MST_TYPE_SYS, 26)
|
||||
#define FW_MST_ID_VEPU0 FW_MST_ID(FW_MST_TYPE_SYS, 27)
|
||||
#define FW_MST_ID_UFSHC FW_MST_ID(FW_MST_TYPE_SYS, 28)
|
||||
#define FW_MST_ID_VDPP FW_MST_ID(FW_MST_TYPE_SYS, 29)
|
||||
#define FW_MST_ID_VICAP FW_MST_ID(FW_MST_TYPE_SYS, 30)
|
||||
#define FW_MST_ID_VOP_M0 FW_MST_ID(FW_MST_TYPE_SYS, 31)
|
||||
#define FW_MST_ID_VOP_M1 FW_MST_ID(FW_MST_TYPE_SYS, 32)
|
||||
#define FW_MST_ID_VPSS FW_MST_ID(FW_MST_TYPE_SYS, 33)
|
||||
#define FW_MST_ID_FSPI0 FW_MST_ID(FW_MST_TYPE_SYS, 34)
|
||||
#define FW_MST_ID_FSPI1 FW_MST_ID(FW_MST_TYPE_SYS, 35)
|
||||
#define FW_MST_ID_BUS_MCU FW_MST_ID(FW_MST_TYPE_SYS, 36)
|
||||
#define FW_MST_ID_DDR_MCU FW_MST_ID(FW_MST_TYPE_SYS, 37)
|
||||
#define FW_MST_ID_NPU_MCU FW_MST_ID(FW_MST_TYPE_SYS, 38)
|
||||
#define FW_MST_ID_CAN0 FW_MST_ID(FW_MST_TYPE_SYS, 39)
|
||||
#define FW_MST_ID_CAN1 FW_MST_ID(FW_MST_TYPE_SYS, 40)
|
||||
#define FW_MST_ID_SDIO FW_MST_ID(FW_MST_TYPE_SYS, 41)
|
||||
#define FW_MST_ID_SDMMC0 FW_MST_ID(FW_MST_TYPE_SYS, 42)
|
||||
#define FW_MST_ID_USB1 FW_MST_ID(FW_MST_TYPE_SYS, 43)
|
||||
#define FW_MST_ID_NPU_M0 FW_MST_ID(FW_MST_TYPE_SYS, 44)
|
||||
#define FW_MST_ID_NPU_M0RO FW_MST_ID(FW_MST_TYPE_SYS, 45)
|
||||
#define FW_MST_ID_NPU_M1 FW_MST_ID(FW_MST_TYPE_SYS, 46)
|
||||
#define FW_MST_ID_NPU_M1RO FW_MST_ID(FW_MST_TYPE_SYS, 47)
|
||||
#define FW_MST_ID_A53_0 FW_MST_ID(FW_MST_TYPE_SYS, 48)
|
||||
#define FW_MST_ID_A53_1 FW_MST_ID(FW_MST_TYPE_SYS, 49)
|
||||
#define FW_MST_ID_A53_2 FW_MST_ID(FW_MST_TYPE_SYS, 50)
|
||||
#define FW_MST_ID_A53_3 FW_MST_ID(FW_MST_TYPE_SYS, 51)
|
||||
#define FW_MST_ID_A72_0 FW_MST_ID(FW_MST_TYPE_SYS, 52)
|
||||
#define FW_MST_ID_A72_1 FW_MST_ID(FW_MST_TYPE_SYS, 53)
|
||||
#define FW_MST_ID_A72_2 FW_MST_ID(FW_MST_TYPE_SYS, 54)
|
||||
#define FW_MST_ID_A72_3 FW_MST_ID(FW_MST_TYPE_SYS, 55)
|
||||
#define FW_MST_ID_DAP_LITE FW_MST_ID(FW_MST_TYPE_SYS, 56)
|
||||
#define FW_MST_ID_VEPU1 FW_MST_ID(FW_MST_TYPE_SYS, 57)
|
||||
#define FW_MST_ID_SYS_CNT 64
|
||||
|
||||
#define FW_MST_ID_PMU_MCU FW_MST_ID(FW_MST_TYPE_PMU, 0)
|
||||
#define FW_MST_ID_VDMA FW_MST_ID(FW_MST_TYPE_PMU, 1)
|
||||
#define FW_MST_ID_PMU_CNT 8
|
||||
|
||||
/* slave id */
|
||||
#define FW_SLV_ID_CAN0 FW_SLV_ID(FW_SLV_TYPE_BUS, 0)
|
||||
#define FW_SLV_ID_CAN1 FW_SLV_ID(FW_SLV_TYPE_BUS, 1)
|
||||
#define FW_SLV_ID_I3C0 FW_SLV_ID(FW_SLV_TYPE_BUS, 2)
|
||||
#define FW_SLV_ID_I3C1 FW_SLV_ID(FW_SLV_TYPE_BUS, 3)
|
||||
#define FW_SLV_ID_BUS_IOC FW_SLV_ID(FW_SLV_TYPE_BUS, 4)
|
||||
#define FW_SLV_ID_COMBO_PIPE_PHY0 FW_SLV_ID(FW_SLV_TYPE_BUS, 5)
|
||||
#define FW_SLV_ID_COMBO_PIPE_PHY1 FW_SLV_ID(FW_SLV_TYPE_BUS, 6)
|
||||
#define FW_SLV_ID_CRU FW_SLV_ID(FW_SLV_TYPE_BUS, 7)
|
||||
#define FW_SLV_ID_DECOM FW_SLV_ID(FW_SLV_TYPE_BUS, 8)
|
||||
#define FW_SLV_ID_CRU_PVTPLL FW_SLV_ID(FW_SLV_TYPE_BUS, 9)
|
||||
#define FW_SLV_ID_I2C1 FW_SLV_ID(FW_SLV_TYPE_BUS, 13)
|
||||
#define FW_SLV_ID_I2C2 FW_SLV_ID(FW_SLV_TYPE_BUS, 14)
|
||||
#define FW_SLV_ID_I2C3 FW_SLV_ID(FW_SLV_TYPE_BUS, 15)
|
||||
#define FW_SLV_ID_I2C4 FW_SLV_ID(FW_SLV_TYPE_BUS, 16)
|
||||
#define FW_SLV_ID_I2C5 FW_SLV_ID(FW_SLV_TYPE_BUS, 17)
|
||||
#define FW_SLV_ID_I2C6 FW_SLV_ID(FW_SLV_TYPE_BUS, 18)
|
||||
#define FW_SLV_ID_I2C7 FW_SLV_ID(FW_SLV_TYPE_BUS, 19)
|
||||
#define FW_SLV_ID_I2C8 FW_SLV_ID(FW_SLV_TYPE_BUS, 20)
|
||||
#define FW_SLV_ID_I2C9 FW_SLV_ID(FW_SLV_TYPE_BUS, 21)
|
||||
#define FW_SLV_ID_INTMUX2BUS FW_SLV_ID(FW_SLV_TYPE_BUS, 22)
|
||||
#define FW_SLV_ID_INTMUX2DDR FW_SLV_ID(FW_SLV_TYPE_BUS, 23)
|
||||
#define FW_SLV_ID_INTMUX2PMU FW_SLV_ID(FW_SLV_TYPE_BUS, 24)
|
||||
#define FW_SLV_ID_PPLL_CRU FW_SLV_ID(FW_SLV_TYPE_BUS, 25)
|
||||
#define FW_SLV_ID_COMBO_PIPE_PHY0_GRF FW_SLV_ID(FW_SLV_TYPE_BUS, 26)
|
||||
#define FW_SLV_ID_COMBO_PIPE_PHY1_GRF FW_SLV_ID(FW_SLV_TYPE_BUS, 27)
|
||||
#define FW_SLV_ID_PMU2 FW_SLV_ID(FW_SLV_TYPE_BUS, 28)
|
||||
#define FW_SLV_ID_SARADC FW_SLV_ID(FW_SLV_TYPE_BUS, 32)
|
||||
#define FW_SLV_ID_SPI0 FW_SLV_ID(FW_SLV_TYPE_BUS, 33)
|
||||
#define FW_SLV_ID_SPI1 FW_SLV_ID(FW_SLV_TYPE_BUS, 34)
|
||||
#define FW_SLV_ID_SPI2 FW_SLV_ID(FW_SLV_TYPE_BUS, 35)
|
||||
#define FW_SLV_ID_SPI3 FW_SLV_ID(FW_SLV_TYPE_BUS, 36)
|
||||
#define FW_SLV_ID_SPI4 FW_SLV_ID(FW_SLV_TYPE_BUS, 37)
|
||||
#define FW_SLV_ID_SYS_GRF FW_SLV_ID(FW_SLV_TYPE_BUS, 38)
|
||||
#define FW_SLV_ID_TSADC FW_SLV_ID(FW_SLV_TYPE_BUS, 41)
|
||||
#define FW_SLV_ID_UART0 FW_SLV_ID(FW_SLV_TYPE_BUS, 42)
|
||||
#define FW_SLV_ID_UART10 FW_SLV_ID(FW_SLV_TYPE_BUS, 43)
|
||||
#define FW_SLV_ID_UART11 FW_SLV_ID(FW_SLV_TYPE_BUS, 44)
|
||||
#define FW_SLV_ID_UART2 FW_SLV_ID(FW_SLV_TYPE_BUS, 45)
|
||||
#define FW_SLV_ID_UART3 FW_SLV_ID(FW_SLV_TYPE_BUS, 46)
|
||||
#define FW_SLV_ID_UART4 FW_SLV_ID(FW_SLV_TYPE_BUS, 47)
|
||||
#define FW_SLV_ID_UART5 FW_SLV_ID(FW_SLV_TYPE_BUS, 48)
|
||||
#define FW_SLV_ID_UART6 FW_SLV_ID(FW_SLV_TYPE_BUS, 49)
|
||||
#define FW_SLV_ID_UART7 FW_SLV_ID(FW_SLV_TYPE_BUS, 50)
|
||||
#define FW_SLV_ID_UART8 FW_SLV_ID(FW_SLV_TYPE_BUS, 51)
|
||||
#define FW_SLV_ID_UART9 FW_SLV_ID(FW_SLV_TYPE_BUS, 52)
|
||||
#define FW_SLV_ID_VCCIO0_1_3_IOC FW_SLV_ID(FW_SLV_TYPE_BUS, 53)
|
||||
#define FW_SLV_ID_VCCIO2_4_5_IOC FW_SLV_ID(FW_SLV_TYPE_BUS, 54)
|
||||
#define FW_SLV_ID_BUS_WDT FW_SLV_ID(FW_SLV_TYPE_BUS, 55)
|
||||
#define FW_SLV_ID_WDT_NS FW_SLV_ID(FW_SLV_TYPE_BUS, 56)
|
||||
#define FW_SLV_ID_DMAC0_NS FW_SLV_ID(FW_SLV_TYPE_BUS, 57)
|
||||
#define FW_SLV_ID_DMAC1_NS FW_SLV_ID(FW_SLV_TYPE_BUS, 58)
|
||||
#define FW_SLV_ID_DMAC2_NS FW_SLV_ID(FW_SLV_TYPE_BUS, 59)
|
||||
#define FW_SLV_ID_DMAC0_S FW_SLV_ID(FW_SLV_TYPE_BUS, 60)
|
||||
#define FW_SLV_ID_DMAC1_S FW_SLV_ID(FW_SLV_TYPE_BUS, 61)
|
||||
#define FW_SLV_ID_DMAC2_S FW_SLV_ID(FW_SLV_TYPE_BUS, 62)
|
||||
#define FW_SLV_ID_GIC400 FW_SLV_ID(FW_SLV_TYPE_BUS, 63)
|
||||
#define FW_SLV_ID_SERVICE_BUS FW_SLV_ID(FW_SLV_TYPE_BUS, 64)
|
||||
#define FW_SLV_ID_SPINLOCK FW_SLV_ID(FW_SLV_TYPE_BUS, 65)
|
||||
#define FW_SLV_ID_MAILBOX_CH0 FW_SLV_ID(FW_SLV_TYPE_BUS, 66)
|
||||
#define FW_SLV_ID_MAILBOX_CH1 FW_SLV_ID(FW_SLV_TYPE_BUS, 67)
|
||||
#define FW_SLV_ID_MAILBOX_CH2 FW_SLV_ID(FW_SLV_TYPE_BUS, 68)
|
||||
#define FW_SLV_ID_MAILBOX_CH3 FW_SLV_ID(FW_SLV_TYPE_BUS, 69)
|
||||
#define FW_SLV_ID_MAILBOX_CH4 FW_SLV_ID(FW_SLV_TYPE_BUS, 70)
|
||||
#define FW_SLV_ID_MAILBOX_CH5 FW_SLV_ID(FW_SLV_TYPE_BUS, 71)
|
||||
#define FW_SLV_ID_MAILBOX_CH6 FW_SLV_ID(FW_SLV_TYPE_BUS, 72)
|
||||
#define FW_SLV_ID_MAILBOX_CH7 FW_SLV_ID(FW_SLV_TYPE_BUS, 73)
|
||||
#define FW_SLV_ID_MAILBOX_CH8 FW_SLV_ID(FW_SLV_TYPE_BUS, 74)
|
||||
#define FW_SLV_ID_MAILBOX_CH9 FW_SLV_ID(FW_SLV_TYPE_BUS, 75)
|
||||
#define FW_SLV_ID_MAILBOX_CH10 FW_SLV_ID(FW_SLV_TYPE_BUS, 76)
|
||||
#define FW_SLV_ID_MAILBOX_CH11 FW_SLV_ID(FW_SLV_TYPE_BUS, 77)
|
||||
#define FW_SLV_ID_MAILBOX_CH12 FW_SLV_ID(FW_SLV_TYPE_BUS, 78)
|
||||
#define FW_SLV_ID_MAILBOX_CH13 FW_SLV_ID(FW_SLV_TYPE_BUS, 79)
|
||||
#define FW_SLV_ID_PWM1_CH0 FW_SLV_ID(FW_SLV_TYPE_BUS, 82)
|
||||
#define FW_SLV_ID_PWM1_CH1 FW_SLV_ID(FW_SLV_TYPE_BUS, 83)
|
||||
#define FW_SLV_ID_PWM1_CH2 FW_SLV_ID(FW_SLV_TYPE_BUS, 84)
|
||||
#define FW_SLV_ID_PWM1_CH3 FW_SLV_ID(FW_SLV_TYPE_BUS, 85)
|
||||
#define FW_SLV_ID_PWM1_CH4 FW_SLV_ID(FW_SLV_TYPE_BUS, 86)
|
||||
#define FW_SLV_ID_PWM1_CH5 FW_SLV_ID(FW_SLV_TYPE_BUS, 87)
|
||||
#define FW_SLV_ID_PWM2_CH0 FW_SLV_ID(FW_SLV_TYPE_BUS, 88)
|
||||
#define FW_SLV_ID_PWM2_CH1 FW_SLV_ID(FW_SLV_TYPE_BUS, 89)
|
||||
#define FW_SLV_ID_PWM2_CH2 FW_SLV_ID(FW_SLV_TYPE_BUS, 90)
|
||||
#define FW_SLV_ID_PWM2_CH3 FW_SLV_ID(FW_SLV_TYPE_BUS, 91)
|
||||
#define FW_SLV_ID_PWM2_CH4 FW_SLV_ID(FW_SLV_TYPE_BUS, 92)
|
||||
#define FW_SLV_ID_PWM2_CH5 FW_SLV_ID(FW_SLV_TYPE_BUS, 93)
|
||||
#define FW_SLV_ID_PWM2_CH6 FW_SLV_ID(FW_SLV_TYPE_BUS, 94)
|
||||
#define FW_SLV_ID_PWM2_CH7 FW_SLV_ID(FW_SLV_TYPE_BUS, 95)
|
||||
#define FW_SLV_ID_TIMER_NS_0_CH0 FW_SLV_ID(FW_SLV_TYPE_BUS, 96)
|
||||
#define FW_SLV_ID_TIMER_NS_0_CH1 FW_SLV_ID(FW_SLV_TYPE_BUS, 97)
|
||||
#define FW_SLV_ID_TIMER_NS_0_CH2 FW_SLV_ID(FW_SLV_TYPE_BUS, 98)
|
||||
#define FW_SLV_ID_TIMER_NS_0_CH3 FW_SLV_ID(FW_SLV_TYPE_BUS, 99)
|
||||
#define FW_SLV_ID_TIMER_NS_0_CH4 FW_SLV_ID(FW_SLV_TYPE_BUS, 100)
|
||||
#define FW_SLV_ID_TIMER_NS_0_CH5 FW_SLV_ID(FW_SLV_TYPE_BUS, 101)
|
||||
#define FW_SLV_ID_TIMER_NS_1_CH0 FW_SLV_ID(FW_SLV_TYPE_BUS, 102)
|
||||
#define FW_SLV_ID_TIMER_NS_1_CH1 FW_SLV_ID(FW_SLV_TYPE_BUS, 103)
|
||||
#define FW_SLV_ID_TIMER_NS_1_CH2 FW_SLV_ID(FW_SLV_TYPE_BUS, 104)
|
||||
#define FW_SLV_ID_TIMER_NS_1_CH3 FW_SLV_ID(FW_SLV_TYPE_BUS, 105)
|
||||
#define FW_SLV_ID_TIMER_NS_1_CH4 FW_SLV_ID(FW_SLV_TYPE_BUS, 106)
|
||||
#define FW_SLV_ID_TIMER_NS_1_CH5 FW_SLV_ID(FW_SLV_TYPE_BUS, 107)
|
||||
#define FW_SLV_ID_GPIO1_CH0 FW_SLV_ID(FW_SLV_TYPE_BUS, 108)
|
||||
#define FW_SLV_ID_GPIO1_CH1 FW_SLV_ID(FW_SLV_TYPE_BUS, 109)
|
||||
#define FW_SLV_ID_GPIO1_CH2 FW_SLV_ID(FW_SLV_TYPE_BUS, 110)
|
||||
#define FW_SLV_ID_GPIO1_CH3 FW_SLV_ID(FW_SLV_TYPE_BUS, 111)
|
||||
#define FW_SLV_ID_GPIO2_CH0 FW_SLV_ID(FW_SLV_TYPE_BUS, 112)
|
||||
#define FW_SLV_ID_GPIO2_CH1 FW_SLV_ID(FW_SLV_TYPE_BUS, 113)
|
||||
#define FW_SLV_ID_GPIO2_CH2 FW_SLV_ID(FW_SLV_TYPE_BUS, 114)
|
||||
#define FW_SLV_ID_GPIO2_CH3 FW_SLV_ID(FW_SLV_TYPE_BUS, 115)
|
||||
#define FW_SLV_ID_GPIO3_CH0 FW_SLV_ID(FW_SLV_TYPE_BUS, 116)
|
||||
#define FW_SLV_ID_GPIO3_CH1 FW_SLV_ID(FW_SLV_TYPE_BUS, 117)
|
||||
#define FW_SLV_ID_GPIO3_CH2 FW_SLV_ID(FW_SLV_TYPE_BUS, 118)
|
||||
#define FW_SLV_ID_GPIO3_CH3 FW_SLV_ID(FW_SLV_TYPE_BUS, 119)
|
||||
#define FW_SLV_ID_GPIO4_CH0 FW_SLV_ID(FW_SLV_TYPE_BUS, 120)
|
||||
#define FW_SLV_ID_GPIO4_CH1 FW_SLV_ID(FW_SLV_TYPE_BUS, 121)
|
||||
#define FW_SLV_ID_GPIO4_CH2 FW_SLV_ID(FW_SLV_TYPE_BUS, 122)
|
||||
#define FW_SLV_ID_GPIO4_CH3 FW_SLV_ID(FW_SLV_TYPE_BUS, 123)
|
||||
#define FW_SLV_ID_BUS_CNT 125
|
||||
|
||||
#define FW_SLV_ID_ACDCDIG_DSM FW_SLV_ID(FW_SLV_TYPE_TOP, 0)
|
||||
#define FW_SLV_ID_ASRC2CH_0 FW_SLV_ID(FW_SLV_TYPE_TOP, 1)
|
||||
#define FW_SLV_ID_ASRC2CH_1 FW_SLV_ID(FW_SLV_TYPE_TOP, 2)
|
||||
#define FW_SLV_ID_ASRC4CH_0 FW_SLV_ID(FW_SLV_TYPE_TOP, 3)
|
||||
#define FW_SLV_ID_ASRC4CH_1 FW_SLV_ID(FW_SLV_TYPE_TOP, 4)
|
||||
#define FW_SLV_ID_PDM1 FW_SLV_ID(FW_SLV_TYPE_TOP, 5)
|
||||
#define FW_SLV_ID_SAI0_8CH FW_SLV_ID(FW_SLV_TYPE_TOP, 6)
|
||||
#define FW_SLV_ID_SAI1_8CH FW_SLV_ID(FW_SLV_TYPE_TOP, 7)
|
||||
#define FW_SLV_ID_SAI2_8CH FW_SLV_ID(FW_SLV_TYPE_TOP, 8)
|
||||
#define FW_SLV_ID_SAI3_2CH FW_SLV_ID(FW_SLV_TYPE_TOP, 9)
|
||||
#define FW_SLV_ID_SAI4_2CH FW_SLV_ID(FW_SLV_TYPE_TOP, 10)
|
||||
#define FW_SLV_ID_SPDIF_RX0 FW_SLV_ID(FW_SLV_TYPE_TOP, 11)
|
||||
#define FW_SLV_ID_SPDIF_RX1 FW_SLV_ID(FW_SLV_TYPE_TOP, 12)
|
||||
#define FW_SLV_ID_SPDIF_TX0 FW_SLV_ID(FW_SLV_TYPE_TOP, 13)
|
||||
#define FW_SLV_ID_SPDIF_TX1 FW_SLV_ID(FW_SLV_TYPE_TOP, 14)
|
||||
#define FW_SLV_ID_DSMC_MEM FW_SLV_ID(FW_SLV_TYPE_TOP, 15)
|
||||
#define FW_SLV_ID_FSPI1 FW_SLV_ID(FW_SLV_TYPE_TOP, 16)
|
||||
#define FW_SLV_ID_FLEXBUS FW_SLV_ID(FW_SLV_TYPE_TOP, 17)
|
||||
#define FW_SLV_ID_SDIO FW_SLV_ID(FW_SLV_TYPE_TOP, 18)
|
||||
#define FW_SLV_ID_SDMMC FW_SLV_ID(FW_SLV_TYPE_TOP, 19)
|
||||
#define FW_SLV_ID_DSMC_CFG FW_SLV_ID(FW_SLV_TYPE_TOP, 20)
|
||||
#define FW_SLV_ID_GMAC0 FW_SLV_ID(FW_SLV_TYPE_TOP, 21)
|
||||
#define FW_SLV_ID_GMAC1 FW_SLV_ID(FW_SLV_TYPE_TOP, 22)
|
||||
#define FW_SLV_ID_SDGMAC_GRF FW_SLV_ID(FW_SLV_TYPE_TOP, 23)
|
||||
#define FW_SLV_ID_EMMC FW_SLV_ID(FW_SLV_TYPE_TOP, 24)
|
||||
#define FW_SLV_ID_FSPI0 FW_SLV_ID(FW_SLV_TYPE_TOP, 25)
|
||||
#define FW_SLV_ID_NSCRYPTO FW_SLV_ID(FW_SLV_TYPE_TOP, 26)
|
||||
#define FW_SLV_ID_RKRNG_NS FW_SLV_ID(FW_SLV_TYPE_TOP, 27)
|
||||
#define FW_SLV_ID_SCRYPTO FW_SLV_ID(FW_SLV_TYPE_TOP, 28)
|
||||
#define FW_SLV_ID_KEYLAD FW_SLV_ID(FW_SLV_TYPE_TOP, 29)
|
||||
#define FW_SLV_ID_RKRNG_S FW_SLV_ID(FW_SLV_TYPE_TOP, 30)
|
||||
#define FW_SLV_ID_OTPC_NS FW_SLV_ID(FW_SLV_TYPE_TOP, 31)
|
||||
#define FW_SLV_ID_JTAG_LOCK FW_SLV_ID(FW_SLV_TYPE_TOP, 33)
|
||||
#define FW_SLV_ID_OTPC_S FW_SLV_ID(FW_SLV_TYPE_TOP, 34)
|
||||
#define FW_SLV_ID_OTPMASK FW_SLV_ID(FW_SLV_TYPE_TOP, 35)
|
||||
#define FW_SLV_ID_SECURE_CRU FW_SLV_ID(FW_SLV_TYPE_TOP, 36)
|
||||
#define FW_SLV_ID_SECURE_CRU_S FW_SLV_ID(FW_SLV_TYPE_TOP, 37)
|
||||
#define FW_SLV_ID_SYS_SGRF FW_SLV_ID(FW_SLV_TYPE_TOP, 38)
|
||||
#define FW_SLV_ID_BOOTROM FW_SLV_ID(FW_SLV_TYPE_TOP, 39)
|
||||
#define FW_SLV_ID_WDT_S FW_SLV_ID(FW_SLV_TYPE_TOP, 41)
|
||||
#define FW_SLV_ID_SERVICE_GMAC FW_SLV_ID(FW_SLV_TYPE_TOP, 42)
|
||||
#define FW_SLV_ID_SERVICE_NVM FW_SLV_ID(FW_SLV_TYPE_TOP, 43)
|
||||
#define FW_SLV_ID_SERVICE_SECURE FW_SLV_ID(FW_SLV_TYPE_TOP, 44)
|
||||
#define FW_SLV_ID_SERVICE_VENC FW_SLV_ID(FW_SLV_TYPE_TOP, 45)
|
||||
#define FW_SLV_ID_SERVICE_VI FW_SLV_ID(FW_SLV_TYPE_TOP, 46)
|
||||
#define FW_SLV_ID_SERVICE_VPU FW_SLV_ID(FW_SLV_TYPE_TOP, 47)
|
||||
#define FW_SLV_ID_VEPU0 FW_SLV_ID(FW_SLV_TYPE_TOP, 48)
|
||||
#define FW_SLV_ID_ISP FW_SLV_ID(FW_SLV_TYPE_TOP, 49)
|
||||
#define FW_SLV_ID_VICAP FW_SLV_ID(FW_SLV_TYPE_TOP, 50)
|
||||
#define FW_SLV_ID_VPSS FW_SLV_ID(FW_SLV_TYPE_TOP, 51)
|
||||
#define FW_SLV_ID_CSIHOST0 FW_SLV_ID(FW_SLV_TYPE_TOP, 52)
|
||||
#define FW_SLV_ID_CSIHOST1 FW_SLV_ID(FW_SLV_TYPE_TOP, 53)
|
||||
#define FW_SLV_ID_CSIHOST2 FW_SLV_ID(FW_SLV_TYPE_TOP, 54)
|
||||
#define FW_SLV_ID_VI_GRF FW_SLV_ID(FW_SLV_TYPE_TOP, 55)
|
||||
#define FW_SLV_ID_EBC FW_SLV_ID(FW_SLV_TYPE_TOP, 56)
|
||||
#define FW_SLV_ID_JPEG FW_SLV_ID(FW_SLV_TYPE_TOP, 57)
|
||||
#define FW_SLV_ID_RGA0 FW_SLV_ID(FW_SLV_TYPE_TOP, 58)
|
||||
#define FW_SLV_ID_RGA1 FW_SLV_ID(FW_SLV_TYPE_TOP, 59)
|
||||
#define FW_SLV_ID_VDPP FW_SLV_ID(FW_SLV_TYPE_TOP, 60)
|
||||
#define FW_SLV_ID_TIMER_S_0_CH0 FW_SLV_ID(FW_SLV_TYPE_TOP, 61)
|
||||
#define FW_SLV_ID_TIMER_S_0_CH1 FW_SLV_ID(FW_SLV_TYPE_TOP, 62)
|
||||
#define FW_SLV_ID_TIMER_S_0_CH2 FW_SLV_ID(FW_SLV_TYPE_TOP, 63)
|
||||
#define FW_SLV_ID_TIMER_S_0_CH3 FW_SLV_ID(FW_SLV_TYPE_TOP, 64)
|
||||
#define FW_SLV_ID_TIMER_S_0_CH4 FW_SLV_ID(FW_SLV_TYPE_TOP, 65)
|
||||
#define FW_SLV_ID_TIMER_S_0_CH5 FW_SLV_ID(FW_SLV_TYPE_TOP, 66)
|
||||
#define FW_SLV_ID_TIMER_S_1_CH0 FW_SLV_ID(FW_SLV_TYPE_TOP, 67)
|
||||
#define FW_SLV_ID_TIMER_S_1_CH1 FW_SLV_ID(FW_SLV_TYPE_TOP, 68)
|
||||
#define FW_SLV_ID_TIMER_S_1_CH2 FW_SLV_ID(FW_SLV_TYPE_TOP, 69)
|
||||
#define FW_SLV_ID_TIMER_S_1_CH3 FW_SLV_ID(FW_SLV_TYPE_TOP, 70)
|
||||
#define FW_SLV_ID_TIMER_S_1_CH4 FW_SLV_ID(FW_SLV_TYPE_TOP, 71)
|
||||
#define FW_SLV_ID_TIMER_S_1_CH5 FW_SLV_ID(FW_SLV_TYPE_TOP, 72)
|
||||
#define FW_SLV_ID_SYS_FW FW_SLV_ID(FW_SLV_TYPE_TOP, 73)
|
||||
#define FW_SLV_ID_VEPU1 FW_SLV_ID(FW_SLV_TYPE_TOP, 75)
|
||||
#define FW_SLV_ID_SERVICE_VEPU1 FW_SLV_ID(FW_SLV_TYPE_TOP, 76)
|
||||
#define FW_SLV_ID_CSIHOST3 FW_SLV_ID(FW_SLV_TYPE_TOP, 77)
|
||||
#define FW_SLV_ID_CSIHOST4 FW_SLV_ID(FW_SLV_TYPE_TOP, 78)
|
||||
#define FW_SLV_ID_TOP_CNT 80
|
||||
|
||||
#define FW_SLV_ID_CENTER_GRF FW_SLV_ID(FW_SLV_TYPE_CENTER, 0)
|
||||
#define FW_SLV_ID_DMA2DDR FW_SLV_ID(FW_SLV_TYPE_CENTER, 1)
|
||||
#define FW_SLV_ID_AHB2APB FW_SLV_ID(FW_SLV_TYPE_CENTER, 2)
|
||||
#define FW_SLV_ID_DDR_GRF FW_SLV_ID(FW_SLV_TYPE_CENTER, 3)
|
||||
#define FW_SLV_ID_DDRCTL0 FW_SLV_ID(FW_SLV_TYPE_CENTER, 4)
|
||||
#define FW_SLV_ID_DDRCTL_1 FW_SLV_ID(FW_SLV_TYPE_CENTER, 5)
|
||||
#define FW_SLV_ID_DDRPHY0 FW_SLV_ID(FW_SLV_TYPE_CENTER, 6)
|
||||
#define FW_SLV_ID_DDR0_CRU FW_SLV_ID(FW_SLV_TYPE_CENTER, 7)
|
||||
#define FW_SLV_ID_DDRPHY1 FW_SLV_ID(FW_SLV_TYPE_CENTER, 8)
|
||||
#define FW_SLV_ID_DDR1_CRU FW_SLV_ID(FW_SLV_TYPE_CENTER, 9)
|
||||
#define FW_SLV_ID_DDRMON0 FW_SLV_ID(FW_SLV_TYPE_CENTER, 10)
|
||||
#define FW_SLV_ID_DDRMON1 FW_SLV_ID(FW_SLV_TYPE_CENTER, 11)
|
||||
#define FW_SLV_ID_HWLP0 FW_SLV_ID(FW_SLV_TYPE_CENTER, 12)
|
||||
#define FW_SLV_ID_HWLP1 FW_SLV_ID(FW_SLV_TYPE_CENTER, 13)
|
||||
#define FW_SLV_ID_DDR_PVTPLL FW_SLV_ID(FW_SLV_TYPE_CENTER, 14)
|
||||
#define FW_SLV_ID_DDR_WDT FW_SLV_ID(FW_SLV_TYPE_CENTER, 15)
|
||||
#define FW_SLV_ID_RKVDEC FW_SLV_ID(FW_SLV_TYPE_CENTER, 16)
|
||||
#define FW_SLV_ID_SERVICE_CCI2 FW_SLV_ID(FW_SLV_TYPE_CENTER, 17)
|
||||
#define FW_SLV_ID_SERVICE_CENTER FW_SLV_ID(FW_SLV_TYPE_CENTER, 18)
|
||||
#define FW_SLV_ID_SERVICE_DDR FW_SLV_ID(FW_SLV_TYPE_CENTER, 19)
|
||||
#define FW_SLV_ID_SERVICE_RKVDEC FW_SLV_ID(FW_SLV_TYPE_CENTER, 20)
|
||||
#define FW_SLV_ID_SERVICE_USB FW_SLV_ID(FW_SLV_TYPE_CENTER, 21)
|
||||
#define FW_SLV_ID_SERVICE_VO0 FW_SLV_ID(FW_SLV_TYPE_CENTER, 22)
|
||||
#define FW_SLV_ID_SERVICE_VO1 FW_SLV_ID(FW_SLV_TYPE_CENTER, 23)
|
||||
#define FW_SLV_ID_SERVICE_VOP FW_SLV_ID(FW_SLV_TYPE_CENTER, 24)
|
||||
#define FW_SLV_ID_UFS_APBS FW_SLV_ID(FW_SLV_TYPE_CENTER, 25)
|
||||
#define FW_SLV_ID_UFS_AXIS FW_SLV_ID(FW_SLV_TYPE_CENTER, 26)
|
||||
#define FW_SLV_ID_USB0 FW_SLV_ID(FW_SLV_TYPE_CENTER, 27)
|
||||
#define FW_SLV_ID_MMU2 FW_SLV_ID(FW_SLV_TYPE_CENTER, 28)
|
||||
#define FW_SLV_ID_USB_GRF FW_SLV_ID(FW_SLV_TYPE_CENTER, 29)
|
||||
#define FW_SLV_ID_HDCP0_MMU FW_SLV_ID(FW_SLV_TYPE_CENTER, 30)
|
||||
#define FW_SLV_ID_SAI5_8CH FW_SLV_ID(FW_SLV_TYPE_CENTER, 31)
|
||||
#define FW_SLV_ID_SAI6_8CH FW_SLV_ID(FW_SLV_TYPE_CENTER, 32)
|
||||
#define FW_SLV_ID_SPDIF_RX2 FW_SLV_ID(FW_SLV_TYPE_CENTER, 33)
|
||||
#define FW_SLV_ID_SPDIF_TX2 FW_SLV_ID(FW_SLV_TYPE_CENTER, 34)
|
||||
#define FW_SLV_ID_HDCP0_KEY FW_SLV_ID(FW_SLV_TYPE_CENTER, 35)
|
||||
#define FW_SLV_ID_DSIHOST FW_SLV_ID(FW_SLV_TYPE_CENTER, 36)
|
||||
#define FW_SLV_ID_EDP0 FW_SLV_ID(FW_SLV_TYPE_CENTER, 37)
|
||||
#define FW_SLV_ID_HDCP0 FW_SLV_ID(FW_SLV_TYPE_CENTER, 38)
|
||||
#define FW_SLV_ID_HDCP0_TRNG FW_SLV_ID(FW_SLV_TYPE_CENTER, 39)
|
||||
#define FW_SLV_ID_HDMITX FW_SLV_ID(FW_SLV_TYPE_CENTER, 40)
|
||||
#define FW_SLV_ID_VO0_GRF FW_SLV_ID(FW_SLV_TYPE_CENTER, 41)
|
||||
#define FW_SLV_ID_EDP0_S FW_SLV_ID(FW_SLV_TYPE_CENTER, 42)
|
||||
#define FW_SLV_ID_HDCP1_MMU FW_SLV_ID(FW_SLV_TYPE_CENTER, 43)
|
||||
#define FW_SLV_ID_SAI7_8CH FW_SLV_ID(FW_SLV_TYPE_CENTER, 44)
|
||||
#define FW_SLV_ID_SPDIF_TX3 FW_SLV_ID(FW_SLV_TYPE_CENTER, 45)
|
||||
#define FW_SLV_ID_HDCP1_KEY FW_SLV_ID(FW_SLV_TYPE_CENTER, 46)
|
||||
#define FW_SLV_ID_DP FW_SLV_ID(FW_SLV_TYPE_CENTER, 47)
|
||||
#define FW_SLV_ID_HDCP1 FW_SLV_ID(FW_SLV_TYPE_CENTER, 48)
|
||||
#define FW_SLV_ID_HDCP1_TRNG FW_SLV_ID(FW_SLV_TYPE_CENTER, 49)
|
||||
#define FW_SLV_ID_VO1_GRF FW_SLV_ID(FW_SLV_TYPE_CENTER, 50)
|
||||
#define FW_SLV_ID_VOP_GRF FW_SLV_ID(FW_SLV_TYPE_CENTER, 52)
|
||||
#define FW_SLV_ID_UFS_GRF FW_SLV_ID(FW_SLV_TYPE_CENTER, 53)
|
||||
#define FW_SLV_ID_SPDIF_TX4 FW_SLV_ID(FW_SLV_TYPE_CENTER, 54)
|
||||
#define FW_SLV_ID_SPDIF_TX5 FW_SLV_ID(FW_SLV_TYPE_CENTER, 55)
|
||||
#define FW_SLV_ID_SAI8_8CH FW_SLV_ID(FW_SLV_TYPE_CENTER, 56)
|
||||
#define FW_SLV_ID_SAI9_8CH FW_SLV_ID(FW_SLV_TYPE_CENTER, 57)
|
||||
#define FW_SLV_ID_DDR_TIMER_CH0 FW_SLV_ID(FW_SLV_TYPE_CENTER, 58)
|
||||
#define FW_SLV_ID_DDR_TIMER_CH1 FW_SLV_ID(FW_SLV_TYPE_CENTER, 59)
|
||||
#define FW_SLV_ID_VOP_RGN0 FW_SLV_ID(FW_SLV_TYPE_CENTER, 60)
|
||||
#define FW_SLV_ID_VOP_RGN1 FW_SLV_ID(FW_SLV_TYPE_CENTER, 61)
|
||||
#define FW_SLV_ID_VOP_RGN2 FW_SLV_ID(FW_SLV_TYPE_CENTER, 62)
|
||||
#define FW_SLV_ID_VOP_RGN3 FW_SLV_ID(FW_SLV_TYPE_CENTER, 63)
|
||||
#define FW_SLV_ID_VOP_OTHERS FW_SLV_ID(FW_SLV_TYPE_CENTER, 64)
|
||||
#define FW_SLV_ID_CENTER_CNT 65
|
||||
|
||||
#define FW_SLV_ID_BIGCORE_CRU FW_SLV_ID(FW_SLV_TYPE_CCI, 0)
|
||||
#define FW_SLV_ID_BIGCORE_GRF FW_SLV_ID(FW_SLV_TYPE_CCI, 1)
|
||||
#define FW_SLV_ID_CCI FW_SLV_ID(FW_SLV_TYPE_CCI, 2)
|
||||
#define FW_SLV_ID_CCI_CRU FW_SLV_ID(FW_SLV_TYPE_CCI, 3)
|
||||
#define FW_SLV_ID_CCI_PVTPLL FW_SLV_ID(FW_SLV_TYPE_CCI, 4)
|
||||
#define FW_SLV_ID_CCI_GRF FW_SLV_ID(FW_SLV_TYPE_CCI, 5)
|
||||
#define FW_SLV_ID_DAP_LITE_A53 FW_SLV_ID(FW_SLV_TYPE_CCI, 6)
|
||||
#define FW_SLV_ID_DAP_LITE_A72 FW_SLV_ID(FW_SLV_TYPE_CCI, 7)
|
||||
#define FW_SLV_ID_LITCORE_GRF FW_SLV_ID(FW_SLV_TYPE_CCI, 8)
|
||||
#define FW_SLV_ID_LITCORE_CRU FW_SLV_ID(FW_SLV_TYPE_CCI, 9)
|
||||
#define FW_SLV_ID_SERVICE_CCI FW_SLV_ID(FW_SLV_TYPE_CCI, 10)
|
||||
#define FW_SLV_ID_BIGCORE_PVTPLL FW_SLV_ID(FW_SLV_TYPE_CCI, 11)
|
||||
#define FW_SLV_ID_LITCORE_PVTPLL FW_SLV_ID(FW_SLV_TYPE_CCI, 12)
|
||||
#define FW_SLV_ID_CCI_CNT 15
|
||||
|
||||
#define FW_SLV_ID_PCIE0_DBI FW_SLV_ID(FW_SLV_TYPE_PHP, 0)
|
||||
#define FW_SLV_ID_PCIE0_DBI_L FW_SLV_ID(FW_SLV_TYPE_PHP, 1)
|
||||
#define FW_SLV_ID_PCIE0_S FW_SLV_ID(FW_SLV_TYPE_PHP, 2)
|
||||
#define FW_SLV_ID_PCIE0_S_L FW_SLV_ID(FW_SLV_TYPE_PHP, 3)
|
||||
#define FW_SLV_ID_PCIE1_DBI FW_SLV_ID(FW_SLV_TYPE_PHP, 4)
|
||||
#define FW_SLV_ID_PCIE1_DBI_L FW_SLV_ID(FW_SLV_TYPE_PHP, 5)
|
||||
#define FW_SLV_ID_PCIE1_S FW_SLV_ID(FW_SLV_TYPE_PHP, 6)
|
||||
#define FW_SLV_ID_PCIE1_S_L FW_SLV_ID(FW_SLV_TYPE_PHP, 7)
|
||||
#define FW_SLV_ID_USB1 FW_SLV_ID(FW_SLV_TYPE_PHP, 8)
|
||||
#define FW_SLV_ID_PCIE0_APB FW_SLV_ID(FW_SLV_TYPE_PHP, 9)
|
||||
#define FW_SLV_ID_PCIE1_APB FW_SLV_ID(FW_SLV_TYPE_PHP, 10)
|
||||
#define FW_SLV_ID_PHP_GRF FW_SLV_ID(FW_SLV_TYPE_PHP, 11)
|
||||
#define FW_SLV_ID_SATA0 FW_SLV_ID(FW_SLV_TYPE_PHP, 12)
|
||||
#define FW_SLV_ID_SATA1 FW_SLV_ID(FW_SLV_TYPE_PHP, 13)
|
||||
#define FW_SLV_ID_SERVICE_PHP FW_SLV_ID(FW_SLV_TYPE_PHP, 14)
|
||||
#define FW_SLV_ID_MMU0 FW_SLV_ID(FW_SLV_TYPE_PHP, 15)
|
||||
#define FW_SLV_ID_MMU1 FW_SLV_ID(FW_SLV_TYPE_PHP, 16)
|
||||
#define FW_SLV_ID_PHP_CNT 20
|
||||
|
||||
#define FW_SLV_ID_GPU_GRF FW_SLV_ID(FW_SLV_TYPE_GPU, 0)
|
||||
#define FW_SLV_ID_GPU FW_SLV_ID(FW_SLV_TYPE_GPU, 1)
|
||||
#define FW_SLV_ID_SERVICE_GPU FW_SLV_ID(FW_SLV_TYPE_GPU, 2)
|
||||
#define FW_SLV_ID_GPU_PVTPLL FW_SLV_ID(FW_SLV_TYPE_GPU, 3)
|
||||
#define FW_SLV_ID_GPU_CNT 5
|
||||
|
||||
#define FW_SLV_ID_RKNN_TOP FW_SLV_ID(FW_SLV_TYPE_NPU, 0)
|
||||
#define FW_SLV_ID_SERVICE_NPU0 FW_SLV_ID(FW_SLV_TYPE_NPU, 1)
|
||||
#define FW_SLV_ID_SERVICE_NPU1 FW_SLV_ID(FW_SLV_TYPE_NPU, 2)
|
||||
#define FW_SLV_ID_SERVICE_NPUSUBSYS FW_SLV_ID(FW_SLV_TYPE_NPU, 3)
|
||||
#define FW_SLV_ID_RKNN_NSP FW_SLV_ID(FW_SLV_TYPE_NPU, 4)
|
||||
#define FW_SLV_ID_NPU_GRF FW_SLV_ID(FW_SLV_TYPE_NPU, 5)
|
||||
#define FW_SLV_ID_NPU_PVTPLL FW_SLV_ID(FW_SLV_TYPE_NPU, 6)
|
||||
#define FW_SLV_ID_NPU_WDT FW_SLV_ID(FW_SLV_TYPE_NPU, 7)
|
||||
#define FW_SLV_ID_NPU_TIMER_CH0 FW_SLV_ID(FW_SLV_TYPE_NPU, 8)
|
||||
#define FW_SLV_ID_NPU_TIMER_CH1 FW_SLV_ID(FW_SLV_TYPE_NPU, 9)
|
||||
#define FW_SLV_ID_NPU_CNT 10
|
||||
|
||||
#define FW_SLV_ID_PDM0 FW_SLV_ID(FW_SLV_TYPE_PMU, 0)
|
||||
#define FW_SLV_ID_PMU_MEM FW_SLV_ID(FW_SLV_TYPE_PMU, 1)
|
||||
#define FW_SLV_ID_CSIDPHY_GRF FW_SLV_ID(FW_SLV_TYPE_PMU, 2)
|
||||
#define FW_SLV_ID_VDMA FW_SLV_ID(FW_SLV_TYPE_PMU, 3)
|
||||
#define FW_SLV_ID_HDPTXPHY FW_SLV_ID(FW_SLV_TYPE_PMU, 4)
|
||||
#define FW_SLV_ID_HDPTXPHY0_GRF FW_SLV_ID(FW_SLV_TYPE_PMU, 5)
|
||||
#define FW_SLV_ID_I2C0 FW_SLV_ID(FW_SLV_TYPE_PMU, 6)
|
||||
#define FW_SLV_ID_DCPHY FW_SLV_ID(FW_SLV_TYPE_PMU, 7)
|
||||
#define FW_SLV_ID_CSIDPHY0 FW_SLV_ID(FW_SLV_TYPE_PMU, 8)
|
||||
#define FW_SLV_ID_DCPHY_GRF FW_SLV_ID(FW_SLV_TYPE_PMU, 9)
|
||||
#define FW_SLV_ID_PMU0 FW_SLV_ID(FW_SLV_TYPE_PMU, 10)
|
||||
#define FW_SLV_ID_PMU0_GRF FW_SLV_ID(FW_SLV_TYPE_PMU, 11)
|
||||
#define FW_SLV_ID_PMU0_IOC FW_SLV_ID(FW_SLV_TYPE_PMU, 12)
|
||||
#define FW_SLV_ID_PMU1 FW_SLV_ID(FW_SLV_TYPE_PMU, 13)
|
||||
#define FW_SLV_ID_PMU1_CRU FW_SLV_ID(FW_SLV_TYPE_PMU, 14)
|
||||
#define FW_SLV_ID_PMU1_CRU_S FW_SLV_ID(FW_SLV_TYPE_PMU, 15)
|
||||
#define FW_SLV_ID_PMU1_GRF FW_SLV_ID(FW_SLV_TYPE_PMU, 16)
|
||||
#define FW_SLV_ID_PMU1_IOC FW_SLV_ID(FW_SLV_TYPE_PMU, 17)
|
||||
#define FW_SLV_ID_PWM0_CH0 FW_SLV_ID(FW_SLV_TYPE_PMU, 18)
|
||||
#define FW_SLV_ID_PWM0_CH1 FW_SLV_ID(FW_SLV_TYPE_PMU, 19)
|
||||
#define FW_SLV_ID_UART1 FW_SLV_ID(FW_SLV_TYPE_PMU, 20)
|
||||
#define FW_SLV_ID_MPHY_GRF FW_SLV_ID(FW_SLV_TYPE_PMU, 21)
|
||||
#define FW_SLV_ID_MPHY FW_SLV_ID(FW_SLV_TYPE_PMU, 22)
|
||||
#define FW_SLV_ID_USB2PHY0_GRF FW_SLV_ID(FW_SLV_TYPE_PMU, 23)
|
||||
#define FW_SLV_ID_USB2PHY1_GRF FW_SLV_ID(FW_SLV_TYPE_PMU, 24)
|
||||
#define FW_SLV_ID_USBDPPHY FW_SLV_ID(FW_SLV_TYPE_PMU, 25)
|
||||
#define FW_SLV_ID_USBDPPHY_GRF FW_SLV_ID(FW_SLV_TYPE_PMU, 26)
|
||||
#define FW_SLV_ID_VCCIO6_IOC FW_SLV_ID(FW_SLV_TYPE_PMU, 27)
|
||||
#define FW_SLV_ID_PMU_WDT FW_SLV_ID(FW_SLV_TYPE_PMU, 28)
|
||||
#define FW_SLV_ID_HPTIMER FW_SLV_ID(FW_SLV_TYPE_PMU, 29)
|
||||
#define FW_SLV_ID_OSC_CHK FW_SLV_ID(FW_SLV_TYPE_PMU, 30)
|
||||
#define FW_SLV_ID_PMU0_SGRF FW_SLV_ID(FW_SLV_TYPE_PMU, 31)
|
||||
#define FW_SLV_ID_PMU1_SGRF FW_SLV_ID(FW_SLV_TYPE_PMU, 32)
|
||||
#define FW_SLV_ID_PMU_PVTM FW_SLV_ID(FW_SLV_TYPE_PMU, 33)
|
||||
#define FW_SLV_ID_SCRAMBLE_KEY FW_SLV_ID(FW_SLV_TYPE_PMU, 34)
|
||||
#define FW_SLV_ID_SERVICE_PMU FW_SLV_ID(FW_SLV_TYPE_PMU, 35)
|
||||
#define FW_SLV_ID_PMU_SRAM_REMAP FW_SLV_ID(FW_SLV_TYPE_PMU, 36)
|
||||
#define FW_SLV_ID_PMU_TIMER_CH0 FW_SLV_ID(FW_SLV_TYPE_PMU, 37)
|
||||
#define FW_SLV_ID_PMU_TIMER_CH1 FW_SLV_ID(FW_SLV_TYPE_PMU, 38)
|
||||
#define FW_SLV_ID_GPIO0_CH0 FW_SLV_ID(FW_SLV_TYPE_PMU, 39)
|
||||
#define FW_SLV_ID_GPIO0_CH1 FW_SLV_ID(FW_SLV_TYPE_PMU, 40)
|
||||
#define FW_SLV_ID_GPIO0_CH2 FW_SLV_ID(FW_SLV_TYPE_PMU, 41)
|
||||
#define FW_SLV_ID_GPIO0_CH3 FW_SLV_ID(FW_SLV_TYPE_PMU, 42)
|
||||
#define FW_SLV_ID_PMU_FW FW_SLV_ID(FW_SLV_TYPE_PMU, 43)
|
||||
#define FW_SLV_ID_PMU_CNT 45
|
||||
|
||||
#define PLAT_MAX_DDR_CAPACITY_MB 0x8000 /* for 32Gb */
|
||||
#define RG_MAP_SECURE(top, base) \
|
||||
(((((top) - 1) & 0x7fff) << 16) | ((base) & 0x7fff))
|
||||
#define RG_MAP_SRAM_SECURE(top_kb, base_kb) \
|
||||
(((((top_kb) / 4 - 1) & 0xff) << 8) | ((base_kb) / 4 & 0xff))
|
||||
#define RG_MAP_CBUF_SECURE(top_kb, base_kb) \
|
||||
(((((top_kb) / 4 - 1) & 0xff) << 8) | ((base_kb) / 4 & 0xff))
|
||||
|
||||
#define FW_UPDATE_WAIT_LOOP 500000
|
||||
|
||||
__pmusramfunc void pmusram_fw_update_msk(uint32_t msk);
|
||||
__pmusramfunc void pmusram_all_fw_bypass(void);
|
||||
|
||||
void fw_init(void);
|
||||
|
||||
#endif /* __FIREWALL_H__ */
|
||||
39
plat/rockchip/rk3576/drivers/secure/secure.c
Normal file
39
plat/rockchip/rk3576/drivers/secure/secure.c
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <secure.h>
|
||||
#include <soc.h>
|
||||
|
||||
static void secure_timer_init(void)
|
||||
{
|
||||
/* gpu's cntvalue comes from stimer1 channel_5 */
|
||||
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
|
||||
TIMER_DIS);
|
||||
|
||||
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_LOAD_COUNT0, 0xffffffff);
|
||||
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_LOAD_COUNT1, 0xffffffff);
|
||||
|
||||
/* auto reload & enable the timer */
|
||||
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
|
||||
TIMER_EN | TIMER_FMODE);
|
||||
}
|
||||
|
||||
void secure_init(void)
|
||||
{
|
||||
secure_timer_init();
|
||||
fw_init();
|
||||
|
||||
/* crypto secure controlled by crypto */
|
||||
mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), BITS_WITH_WMASK(0, 0x1, 4));
|
||||
mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), BITS_WITH_WMASK(0, 0x1, 5));
|
||||
|
||||
/* disable DP encryption mode */
|
||||
mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(1), BITS_WITH_WMASK(1, 0x1, 14));
|
||||
}
|
||||
30
plat/rockchip/rk3576/drivers/secure/secure.h
Normal file
30
plat/rockchip/rk3576/drivers/secure/secure.h
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef SECURE_H
|
||||
#define SECURE_H
|
||||
|
||||
#include <firewall.h>
|
||||
|
||||
/* PMU0SGRF */
|
||||
#define PMU0SGRF_SOC_CON(i) ((i) * 4)
|
||||
|
||||
/* PMU1SGRF */
|
||||
#define PMU1SGRF_SOC_CON(i) ((i) * 4)
|
||||
|
||||
/* CCISGRF */
|
||||
#define CCISGRF_SOC_CON(i) (0x20 + (i) * 4)
|
||||
#define CCISGRF_DDR_HASH_CON(i) (0x40 + (i) * 4)
|
||||
|
||||
/* SGRF */
|
||||
#define SYSSGRF_DDR_BANK_MSK(i) (0x04 + (i) * 4)
|
||||
#define SYSSGRF_DDR_CH_MSK(i) (0x18 + (i) * 4)
|
||||
#define SYSSGRF_SOC_CON(i) (0x20 + (i) * 4)
|
||||
#define SYSSGRF_DMAC_CON(i) (0x80 + (i) * 4)
|
||||
#define SYSSGRF_SOC_STATUS 0x240
|
||||
|
||||
void secure_init(void);
|
||||
|
||||
#endif /* SECURE_H */
|
||||
129
plat/rockchip/rk3576/drivers/soc/soc.c
Normal file
129
plat/rockchip/rk3576/drivers/soc/soc.c
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <bl31/bl31.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/console.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/xlat_tables/xlat_tables_compat.h>
|
||||
#include <platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <pmu.h>
|
||||
|
||||
#include <plat_private.h>
|
||||
#include <rk3576_clk.h>
|
||||
#include <secure.h>
|
||||
#include <soc.h>
|
||||
|
||||
const mmap_region_t plat_rk_mmap[] = {
|
||||
MAP_REGION_FLAT(RK3576_DEV_RNG0_BASE, RK3576_DEV_RNG0_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(DDR_SHARE_MEM, DDR_SHARE_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_NS),
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
/* The RockChip power domain tree descriptor */
|
||||
const unsigned char rockchip_power_domain_tree_desc[] = {
|
||||
/* No of root nodes */
|
||||
PLATFORM_SYSTEM_COUNT,
|
||||
/* No of children for the root node */
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
/* No of children for the first cluster node */
|
||||
PLATFORM_CLUSTER0_CORE_COUNT,
|
||||
/* No of children for the second cluster node */
|
||||
PLATFORM_CLUSTER1_CORE_COUNT
|
||||
};
|
||||
|
||||
static void clear_glb_reset_status(void)
|
||||
{
|
||||
uint32_t cru_sel55 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(55));
|
||||
|
||||
/* switch pclk_bus_root to 24M before writing CRU_GLB_RST_ST */
|
||||
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(55),
|
||||
BITS_WITH_WMASK(2, 0x3, 2));
|
||||
dsb();
|
||||
|
||||
mmio_write_32(CRU_BASE + CRU_GLB_RST_ST, 0xffff);
|
||||
dsb();
|
||||
|
||||
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(55),
|
||||
WITH_16BITS_WMSK(cru_sel55));
|
||||
}
|
||||
|
||||
static void print_glb_reset_status(void)
|
||||
{
|
||||
uint32_t glb_rst_st = 0, warm_boot = 0;
|
||||
|
||||
/* clear CRU_GLB_RST_ST_NCLR if cold boot */
|
||||
if (mmio_read_32(PMU0_GRF_BASE + PMU0GRF_OS_REG(17)) == WARM_BOOT_MAGIC) {
|
||||
/* ignore npu_wdt*/
|
||||
glb_rst_st = mmio_read_32(CRU_BASE + CRU_GLB_RST_ST_NCLR) & VALID_GLB_RST_MSK;
|
||||
warm_boot = 1;
|
||||
} else {
|
||||
mmio_write_32(PMU0_GRF_BASE + PMU0GRF_OS_REG(17), WARM_BOOT_MAGIC);
|
||||
}
|
||||
|
||||
clear_glb_reset_status();
|
||||
|
||||
/* save glb_rst_st in mem_os_reg31 */
|
||||
write_mem_os_reg(31, glb_rst_st);
|
||||
|
||||
if (warm_boot != 0)
|
||||
INFO("soc warm boot, reset status: 0x%x\n", glb_rst_st);
|
||||
else
|
||||
INFO("soc cold boot\n");
|
||||
}
|
||||
|
||||
static void system_reset_init(void)
|
||||
{
|
||||
/*
|
||||
* enable tsadc trigger global reset and select first reset.
|
||||
* enable global reset and wdt trigger pmu reset.
|
||||
* select first reset trigger pmu reset.
|
||||
*/
|
||||
mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 0xffdf);
|
||||
|
||||
/* enable wdt_s reset */
|
||||
mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), 0x20002000);
|
||||
|
||||
/* enable wdt_ns reset */
|
||||
mmio_write_32(SYS_GRF_BASE + SYSGRF_SOC_CON(4), 0x01000100);
|
||||
|
||||
/* reset width = 0xffff */
|
||||
mmio_write_32(PMU1_GRF_BASE + PMU1GRF_SOC_CON(6), 0xffffffff);
|
||||
|
||||
/* enable first/tsadc/wdt reset output */
|
||||
mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(0), 0x00070007);
|
||||
|
||||
/* pmu0sgrf pmu0_ioc hold */
|
||||
mmio_write_32(PMU0SGRF_BASE + PMU1SGRF_SOC_CON(0), 0xffff1800);
|
||||
|
||||
/* pmu1sgrf pmu1_grf hold */
|
||||
mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(16), 0xffff8800);
|
||||
|
||||
/* select tsadc_shut_m0 ionmux*/
|
||||
mmio_write_32(PMU0_IOC_BASE + 0x0, 0x00f00090);
|
||||
|
||||
print_glb_reset_status();
|
||||
}
|
||||
|
||||
void plat_rockchip_soc_init(void)
|
||||
{
|
||||
rockchip_clock_init();
|
||||
system_reset_init();
|
||||
secure_init();
|
||||
rockchip_init_scmi_server();
|
||||
|
||||
/* release cpu1~cpu7 */
|
||||
mmio_write_32(CCI_GRF_BASE + CCIGRF_CON(4), 0xffffffff);
|
||||
mmio_write_32(LITCORE_GRF_BASE + COREGRF_CPU_CON(1),
|
||||
BITS_WITH_WMASK(0x77, 0xff, 4));
|
||||
}
|
||||
271
plat/rockchip/rk3576/drivers/soc/soc.h
Normal file
271
plat/rockchip/rk3576/drivers/soc/soc.h
Normal file
|
|
@ -0,0 +1,271 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_H__
|
||||
#define __SOC_H__
|
||||
|
||||
enum pll_id {
|
||||
APLL_ID,
|
||||
CPLL_ID,
|
||||
DPLL_ID,
|
||||
GPLL_ID,
|
||||
};
|
||||
|
||||
enum cru_mode_con00 {
|
||||
CLK_APLL,
|
||||
CLK_CPLL,
|
||||
CLK_GPLL,
|
||||
CLK_DPLL,
|
||||
};
|
||||
|
||||
#define KHz 1000
|
||||
#define MHz (1000 * KHz)
|
||||
#define OSC_HZ (24 * MHz)
|
||||
|
||||
#define MCU_VALID_START_ADDRESS 0x800000
|
||||
|
||||
/* CRU */
|
||||
#define GLB_SRST_FST_CFG_VAL 0xfdb9
|
||||
|
||||
#define CRU_PLLS_CON(pll_id, i) ((pll_id) * 0x20 + (i) * 0x4)
|
||||
#define CRU_PLL_CON(i) ((i) * 0x4)
|
||||
#define CRU_MODE_CON 0x280
|
||||
#define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
|
||||
#define CRU_CLKSEL_CON_CNT 181
|
||||
#define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
|
||||
#define CRU_CLKGATE_CON_CNT 80
|
||||
#define CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
|
||||
#define CRU_SOFTRST_CON_CNT 80
|
||||
|
||||
#define CRU_GLB_CNT_TH 0xc00
|
||||
#define CRU_GLB_RST_ST 0xc04
|
||||
#define CRU_GLB_SRST_FST 0xc08
|
||||
#define CRU_GLB_SRST_SND 0xc0c
|
||||
#define CRU_GLB_RST_CON 0xc10
|
||||
#define CRU_GLB_RST_ST_NCLR 0xc14
|
||||
#define CRU_LITCOREWFI_CON0 0xc40
|
||||
#define CRU_BIGCOREWFI_CON0 0xc44
|
||||
#define CRU_NON_SECURE_GT_CON0 0xc48
|
||||
|
||||
#define CRU_PLLCON0_M_MASK 0x3ff
|
||||
#define CRU_PLLCON0_M_SHIFT 0
|
||||
#define CRU_PLLCON1_P_MASK 0x3f
|
||||
#define CRU_PLLCON1_P_SHIFT 0
|
||||
#define CRU_PLLCON1_S_MASK 0x7
|
||||
#define CRU_PLLCON1_S_SHIFT 6
|
||||
#define CRU_PLLCON2_K_MASK 0xffff
|
||||
#define CRU_PLLCON2_K_SHIFT 0
|
||||
#define CRU_PLLCON1_PWRDOWN BIT(13)
|
||||
#define CRU_PLLCON6_LOCK_STATUS BIT(15)
|
||||
|
||||
/* LCORE_CRU */
|
||||
#define LCORE_CRU_MODE_CON 0x280
|
||||
#define LCORE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
|
||||
#define LCORE_CRU_CLKSEL_CON_CNT 4
|
||||
#define LCORE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
|
||||
#define LCORE_CRU_CLKGATE_CON_CNT 2
|
||||
#define LCORE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
|
||||
#define LCORE_CRU_SOFTRST_CON_CNT 4
|
||||
|
||||
/* BCORE_CRU */
|
||||
#define BCORE_CRU_MODE_CON 0x280
|
||||
#define BCORE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
|
||||
#define BCORE_CRU_CLKSEL_CON_CNT 5
|
||||
#define BCORE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
|
||||
#define BCORE_CRU_CLKGATE_CON_CNT 3
|
||||
#define BCORE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
|
||||
#define BCORE_CRU_SOFTRST_CON_CNT 4
|
||||
|
||||
/* DDRCRU */
|
||||
#define DDRCRU_MODE_CON 0x280
|
||||
#define DDRCRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
|
||||
#define DDRCRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
|
||||
#define DDRCRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
|
||||
|
||||
/* CCICRU */
|
||||
#define CCICRU_MODE_CON 0x280
|
||||
#define CCICRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
|
||||
#define CCICRU_CLKSEL_CON_CNT 10
|
||||
#define CCICRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
|
||||
#define CCICRU_CLKGATE_CON_CNT 7
|
||||
#define CCICRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
|
||||
#define CCICRU_SOFTRST_CON_CNT 7
|
||||
|
||||
/* CRU AUTOCS */
|
||||
#define CRU_AUTOCS_CON(offset) (CRU_BASE + (offset))
|
||||
#define CRU_AUTOCS_SEC_CON(offset) (SECURE_CRU_BASE + (offset))
|
||||
#define CRU_AUTOCS_CCI_CON(offset) (CCI_CRU_BASE + (offset))
|
||||
#define AUTOCS_EN_BIT BIT(12)
|
||||
|
||||
/* PHP_CRU */
|
||||
#define PHP_CRU_MODE_CON 0x280
|
||||
#define PHP_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
|
||||
#define PHP_CRU_CLKSEL_CON_CNT 2
|
||||
#define PHP_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
|
||||
#define PHP_CRU_CLKGATE_CON_CNT 2
|
||||
#define PHP_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
|
||||
#define PHP_CRU_SOFTRST_CON_CNT 2
|
||||
|
||||
/* SECURE CRU */
|
||||
#define SECURE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
|
||||
#define SECURE_CRU_CLKSEL_CON_CNT 1
|
||||
#define SECURE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
|
||||
#define SECURE_CRU_CLKGATE_CON_CNT 1
|
||||
#define SECURE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
|
||||
#define SECURE_CRU_SOFTRST_CON_CNT 1
|
||||
|
||||
/* SECURE SCRU */
|
||||
#define SECURE_SCRU_CLKSEL_CON(i) ((i) * 0x4 + 0x4000)
|
||||
#define SECURE_SCRU_CLKSEL_CON_CNT 7
|
||||
#define SECURE_SCRU_CLKGATE_CON(i) ((i) * 0x4 + 0x4028)
|
||||
#define SECURE_SCRU_CLKGATE_CON_CNT 6
|
||||
#define SECURE_SCRU_SOFTRST_CON(i) ((i) * 0x4 + 0x4050)
|
||||
#define SECURE_SCRU_SOFTRST_CON_CNT 6
|
||||
#define SECURE_SCRU_MODE_CON 0x4280
|
||||
|
||||
/* SYSGRF */
|
||||
#define SYSGRF_SOC_CON(i) ((i) * 4)
|
||||
#define SYSGRF_SOC_STATUS 0x30
|
||||
#define SYSGRF_NOC_CON(i) (0x40 + (i) * 4)
|
||||
#define SYSGRF_NOC_STATUS(i) (0x60 + (i) * 4)
|
||||
#define SYSGRF_MEM_CON(i) (0x80 + (i) * 4)
|
||||
#define SYSGRF_STATUS0 0x140
|
||||
#define SYSGRF_STATUS1 0x144
|
||||
|
||||
/* COREGRF */
|
||||
#define COREGRF_SOC_STATUS(i) (0x2c + (i) * 4)
|
||||
#define COREGRF_CPU_CON(i) (0x34 + (i) * 4)
|
||||
|
||||
/* DDRGRF */
|
||||
#define DDRGRF_CHA_CON(i) ((i) * 4)
|
||||
#define DDRGRF_CHB_CON(i) (0x100 + (i) * 4)
|
||||
#define DDRGRF_CHA_ST(i) (0x60 + (i) * 4)
|
||||
#define DDRGRF_CHB_ST(i) (0xb0 + (i) * 4)
|
||||
#define DDRGRF_CON(i) (0x140 + (i) * 4)
|
||||
|
||||
/* CCIGRF */
|
||||
#define CCIGRF_CON(i) ((i) * 4)
|
||||
#define CCIGRF_STATUS(i) (0x34 + (i) * 4)
|
||||
|
||||
/* IOC */
|
||||
#define VCCIO_IOC_MISC_CON(i) (0x400 + (i) * 4)
|
||||
|
||||
/* pvtm */
|
||||
#define PVTM_CON(i) (0x4 + (i) * 4)
|
||||
#define PVTM_INTEN 0x70
|
||||
#define PVTM_INTSTS 0x74
|
||||
#define PVTM_STATUS(i) (0x80 + (i) * 4)
|
||||
#define PVTM_CALC_CNT 0x200
|
||||
|
||||
enum pvtm_con0 {
|
||||
pvtm_start = 0,
|
||||
pvtm_osc_en = 1,
|
||||
pvtm_osc_sel = 2,
|
||||
pvtm_rnd_seed_en = 5,
|
||||
};
|
||||
|
||||
/* WDT */
|
||||
#define WDT_CR 0x0
|
||||
#define WDT_TORR 0x4
|
||||
#define WDT_CCVR 0x8
|
||||
#define WDT_CRR 0xc
|
||||
#define WDT_STAT 0x10
|
||||
#define WDT_EOI 0x14
|
||||
|
||||
#define WDT_EN BIT(0)
|
||||
#define WDT_RSP_MODE BIT(1)
|
||||
|
||||
/* timer */
|
||||
#define TIMER_LOAD_COUNT0 0x00
|
||||
#define TIMER_LOAD_COUNT1 0x04
|
||||
#define TIMER_CURRENT_VALUE0 0x08
|
||||
#define TIMER_CURRENT_VALUE1 0x0c
|
||||
#define TIMER_CONTROL_REG 0x10
|
||||
#define TIMER_INTSTATUS 0x18
|
||||
|
||||
#define TIMER_DIS 0x0
|
||||
#define TIMER_EN 0x1
|
||||
|
||||
#define TIMER_FMODE (0x0 << 1)
|
||||
#define TIMER_RMODE (0x1 << 1)
|
||||
|
||||
/* hp timer */
|
||||
#define TIMER_HP_REVISION 0x00
|
||||
#define TIMER_HP_CTRL 0x04
|
||||
#define TIMER_HP_INTR_EN 0x08
|
||||
#define TIMER_HP_T24_GCD 0x0c
|
||||
#define TIMER_HP_T32_GCD 0x10
|
||||
#define TIMER_HP_LOAD_COUNT0 0x14
|
||||
#define TIMER_HP_LOAD_COUNT1 0x18
|
||||
#define TIMER_HP_T24_DELAT_COUNT0 0x1c
|
||||
#define TIMER_HP_T24_DELAT_COUNT1 0x20
|
||||
#define TIMER_HP_CURR_32K_VALUE0 0x24
|
||||
#define TIMER_HP_CURR_32K_VALUE1 0x28
|
||||
#define TIMER_HP_CURR_TIMER_VALUE0 0x2c
|
||||
#define TIMER_HP_CURR_TIMER_VALUE1 0x30
|
||||
#define TIMER_HP_T24_32BEGIN0 0x34
|
||||
#define TIMER_HP_T24_32BEGIN1 0x38
|
||||
#define TIMER_HP_T32_24END0 0x3c
|
||||
#define TIMER_HP_T32_24END1 0x40
|
||||
#define TIMER_HP_BEGIN_END_VALID 0x44
|
||||
#define TIMER_HP_SYNC_REQ 0x48
|
||||
#define TIMER_HP_INTR_STATUS 0x4c
|
||||
#define TIMER_HP_UPD_EN 0x50
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_SWPORT_DR_L 0x0000
|
||||
#define GPIO_SWPORT_DR_H 0x0004
|
||||
#define GPIO_SWPORT_DDR_L 0x0008
|
||||
#define GPIO_SWPORT_DDR_H 0x000c
|
||||
#define GPIO_INT_EN_L 0x0010
|
||||
#define GPIO_INT_EN_H 0x0014
|
||||
#define GPIO_INT_MASK_L 0x0018
|
||||
#define GPIO_INT_MASK_H 0x001c
|
||||
#define GPIO_INT_TYPE_L 0x0020
|
||||
#define GPIO_INT_TYPE_H 0x0024
|
||||
#define GPIO_INT_POLARITY_L 0x0028
|
||||
#define GPIO_INT_POLARITY_H 0x002c
|
||||
#define GPIO_INT_BOTHEDGE_L 0x0030
|
||||
#define GPIO_INT_BOTHEDGE_H 0x0034
|
||||
#define GPIO_DEBOUNCE_L 0x0038
|
||||
#define GPIO_DEBOUNCE_H 0x003c
|
||||
#define GPIO_DBCLK_DIV_EN_L 0x0040
|
||||
#define GPIO_DBCLK_DIV_EN_H 0x0044
|
||||
#define GPIO_DBCLK_DIV_CON 0x0048
|
||||
#define GPIO_INT_STATUS 0x0050
|
||||
#define GPIO_INT_RAWSTATUS 0x0058
|
||||
#define GPIO_PORT_EOI_L 0x0060
|
||||
#define GPIO_PORT_EOI_H 0x0064
|
||||
#define GPIO_EXT_PORT 0x0070
|
||||
#define GPIO_VER_ID 0x0078
|
||||
#define GPIO_STORE_ST_L 0x0080
|
||||
#define GPIO_STORE_ST_H 0x0084
|
||||
#define GPIO_REG_GROUP_L 0x0100
|
||||
#define GPIO_REG_GROUP_H 0x0104
|
||||
#define GPIO_VIRTUAL_EN 0x0108
|
||||
#define GPIO_REG_GROUP1_L 0x0110
|
||||
#define GPIO_REG_GROUP1_H 0x0114
|
||||
#define GPIO_REG_GROUP2_L 0x0118
|
||||
#define GPIO_REG_GROUP2_H 0x011c
|
||||
#define GPIO_REG_GROUP3_L 0x0120
|
||||
#define GPIO_REG_GROUP3_H 0x0124
|
||||
|
||||
/* PWM */
|
||||
#define PMW_PWRCAPTURE_VAL 0x15c
|
||||
|
||||
#define SOC_RK3576A1 0x35760101
|
||||
#define SOC_RK3576J1 0x35760a01
|
||||
#define SOC_RK3576M1 0x35760d01
|
||||
#define SOC_RK3576S1 0x35761301
|
||||
#define SOC_UNKNOWN 0xeeee
|
||||
#define SOC_ROOT 0x0
|
||||
|
||||
int rk_soc_is_(uint32_t soc_id);
|
||||
uint32_t timer_hp_get_freq(void);
|
||||
int soc_bus_div_sip_handler(uint32_t id, uint32_t cfg, uint32_t enable_msk);
|
||||
void autocs_suspend(void);
|
||||
void autocs_resume(void);
|
||||
|
||||
#endif /* __SOC_H__ */
|
||||
40
plat/rockchip/rk3576/include/plat.ld.S
Normal file
40
plat/rockchip/rk3576/include/plat.ld.S
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef ROCKCHIP_PLAT_LD_S
|
||||
#define ROCKCHIP_PLAT_LD_S
|
||||
|
||||
MEMORY {
|
||||
PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = PMUSRAM_BASE;
|
||||
|
||||
/*
|
||||
* pmu_cpuson_entrypoint request address
|
||||
* align 64K when resume, so put it in the
|
||||
* start of pmusram
|
||||
*/
|
||||
.text_pmusram : {
|
||||
ASSERT(. == ALIGN(64 * 1024),
|
||||
".pmusram.entry request 64K aligned.");
|
||||
KEEP(*(.pmusram.entry))
|
||||
__bl31_pmusram_text_start = .;
|
||||
*(.pmusram.text)
|
||||
*(.pmusram.rodata)
|
||||
. = ALIGN(PAGE_SIZE);
|
||||
__bl31_pmusram_text_end = .;
|
||||
__bl31_pmusram_data_start = .;
|
||||
*(.pmusram.data)
|
||||
. = ALIGN(PAGE_SIZE);
|
||||
__bl31_pmusram_data_end = .;
|
||||
|
||||
ASSERT(__bl31_pmusram_data_end <= PMUSRAM_BASE + PMUSRAM_RSIZE,
|
||||
".pmusram has exceeded its limit.");
|
||||
} >PMUSRAM
|
||||
}
|
||||
#endif /* ROCKCHIP_PLAT_LD_S */
|
||||
11
plat/rockchip/rk3576/include/plat_sip_calls.h
Normal file
11
plat/rockchip/rk3576/include/plat_sip_calls.h
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_SIP_CALLS_H__
|
||||
#define __PLAT_SIP_CALLS_H__
|
||||
|
||||
#define RK_PLAT_SIP_NUM_CALLS 0
|
||||
|
||||
#endif /* __PLAT_SIP_CALLS_H__ */
|
||||
116
plat/rockchip/rk3576/include/platform_def.h
Normal file
116
plat/rockchip/rk3576/include/platform_def.h
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_DEF_H__
|
||||
#define __PLATFORM_DEF_H__
|
||||
|
||||
#include <arch.h>
|
||||
#include <common_def.h>
|
||||
#include <rk3576_def.h>
|
||||
|
||||
#define DEBUG_XLAT_TABLE 0
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform binary types for linking
|
||||
******************************************************************************/
|
||||
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
|
||||
#define PLATFORM_LINKER_ARCH aarch64
|
||||
|
||||
/*******************************************************************************
|
||||
* Generic platform constants
|
||||
******************************************************************************/
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#if DEBUG_XLAT_TABLE
|
||||
#define PLATFORM_STACK_SIZE 0x800
|
||||
#elif IMAGE_BL1
|
||||
#define PLATFORM_STACK_SIZE 0x440
|
||||
#elif IMAGE_BL2
|
||||
#define PLATFORM_STACK_SIZE 0x400
|
||||
#elif IMAGE_BL31
|
||||
#define PLATFORM_STACK_SIZE 0x800
|
||||
#elif IMAGE_BL32
|
||||
#define PLATFORM_STACK_SIZE 0x440
|
||||
#endif
|
||||
|
||||
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
|
||||
|
||||
#define PLATFORM_SYSTEM_COUNT 1
|
||||
#define PLATFORM_CLUSTER_COUNT 2
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT 4
|
||||
#define PLATFORM_CLUSTER1_CORE_COUNT 4
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
|
||||
PLATFORM_CLUSTER0_CORE_COUNT)
|
||||
|
||||
#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
|
||||
PLATFORM_CLUSTER_COUNT + \
|
||||
PLATFORM_CORE_COUNT)
|
||||
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
|
||||
|
||||
#define PLAT_RK_CLST_TO_CPUID_SHIFT 6
|
||||
|
||||
/*
|
||||
* This macro defines the deepest retention state possible. A higher state
|
||||
* id will represent an invalid or a power down state.
|
||||
*/
|
||||
#define PLAT_MAX_RET_STATE 1
|
||||
|
||||
/*
|
||||
* This macro defines the deepest power down states possible. Any state ID
|
||||
* higher than this is invalid.
|
||||
*/
|
||||
#define PLAT_MAX_OFF_STATE 2
|
||||
/*******************************************************************************
|
||||
* Platform memory map related constants
|
||||
******************************************************************************/
|
||||
/* TF txet, ro, rw, Size: 512KB */
|
||||
#define TZRAM_BASE RK_DRAM_BASE
|
||||
#define TZRAM_SIZE 0x100000
|
||||
|
||||
/*******************************************************************************
|
||||
* BL31 specific defines.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Put BL3-1 at the top of the Trusted RAM
|
||||
*/
|
||||
#define BL31_BASE (TZRAM_BASE + 0x40000)
|
||||
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
|
||||
#define ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define MAX_XLAT_TABLES 18
|
||||
#define MAX_MMAP_REGIONS 27
|
||||
|
||||
/*******************************************************************************
|
||||
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
||||
* aligned on the biggest cache line size in the platform. This is known only
|
||||
* to the platform as it might have a combination of integrated and external
|
||||
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
|
||||
* line at any cache level. They could belong to different cpus/clusters &
|
||||
* get written while being protected by different locks causing corruption of
|
||||
* a valid mailbox address.
|
||||
******************************************************************************/
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
/*
|
||||
* Define GICD and GICC and GICR base
|
||||
*/
|
||||
#define PLAT_RK_GICD_BASE PLAT_GICD_BASE
|
||||
#define PLAT_RK_GICC_BASE PLAT_GICC_BASE
|
||||
#define PLAT_RK_GICR_BASE PLAT_GICR_BASE
|
||||
|
||||
#define PLAT_RK_UART_BASE RK_DBG_UART_BASE
|
||||
#define PLAT_RK_UART_CLOCK RK_DBG_UART_CLOCK
|
||||
#define PLAT_RK_UART_BAUDRATE RK_DBG_UART_BAUDRATE
|
||||
|
||||
#define PLAT_RK_PRIMARY_CPU 0x0
|
||||
#endif /* __PLATFORM_DEF_H__ */
|
||||
31
plat/rockchip/rk3576/plat_sip_calls.c
Normal file
31
plat/rockchip/rk3576/plat_sip_calls.c
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <common/runtime_svc.h>
|
||||
#include <drivers/scmi-msg.h>
|
||||
|
||||
#include <plat_sip_calls.h>
|
||||
#include <rockchip_sip_svc.h>
|
||||
|
||||
uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
u_register_t flags)
|
||||
{
|
||||
switch (smc_fid) {
|
||||
case RK_SIP_SCMI_AGENT0:
|
||||
scmi_smt_fastcall_smc_entry(0);
|
||||
SMC_RET1(handle, 0);
|
||||
|
||||
default:
|
||||
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
}
|
||||
}
|
||||
115
plat/rockchip/rk3576/platform.mk
Normal file
115
plat/rockchip/rk3576/platform.mk
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
#
|
||||
# Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
RK_PLAT := plat/rockchip
|
||||
RK_PLAT_SOC := ${RK_PLAT}/${PLAT}
|
||||
RK_PLAT_COMMON := ${RK_PLAT}/common
|
||||
|
||||
DISABLE_BIN_GENERATION := 1
|
||||
|
||||
include drivers/arm/gic/v2/gicv2.mk
|
||||
include lib/libfdt/libfdt.mk
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
||||
PLAT_INCLUDES := -Idrivers/arm/gic/common/ \
|
||||
-Idrivers/arm/gic/v2/ \
|
||||
-Idrivers/scmi-msg/ \
|
||||
-Iinclude/bl31 \
|
||||
-Iinclude/common \
|
||||
-Iinclude/drivers \
|
||||
-Iinclude/drivers/arm \
|
||||
-Iinclude/drivers/io \
|
||||
-Iinclude/drivers/ti/uart \
|
||||
-Iinclude/lib \
|
||||
-Iinclude/lib/cpus/${ARCH} \
|
||||
-Iinclude/lib/el3_runtime \
|
||||
-Iinclude/lib/psci \
|
||||
-Iinclude/plat/common \
|
||||
-Iinclude/services \
|
||||
-I${RK_PLAT_COMMON}/ \
|
||||
-I${RK_PLAT_COMMON}/pmusram/ \
|
||||
-I${RK_PLAT_COMMON}/include/ \
|
||||
-I${RK_PLAT_COMMON}/drivers/pmu/ \
|
||||
-I${RK_PLAT_COMMON}/drivers/parameter/ \
|
||||
-I${RK_PLAT_COMMON}/scmi/ \
|
||||
-I${RK_PLAT_SOC}/ \
|
||||
-I${RK_PLAT_SOC}/drivers/dmc/ \
|
||||
-I${RK_PLAT_SOC}/drivers/pmu/ \
|
||||
-I${RK_PLAT_SOC}/drivers/secure/ \
|
||||
-I${RK_PLAT_SOC}/drivers/soc/ \
|
||||
-I${RK_PLAT_SOC}/include/ \
|
||||
-I${RK_PLAT_SOC}/scmi/
|
||||
|
||||
RK_GIC_SOURCES := ${GICV2_SOURCES} \
|
||||
plat/common/plat_gicv2.c \
|
||||
${RK_PLAT}/common/rockchip_gicv2.c
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := ${XLAT_TABLES_LIB_SRCS} \
|
||||
common/desc_image_load.c \
|
||||
lib/bl_aux_params/bl_aux_params.c \
|
||||
plat/common/aarch64/crash_console_helpers.S \
|
||||
plat/common/plat_psci_common.c
|
||||
|
||||
ifneq (${ENABLE_STACK_PROTECTOR},0)
|
||||
PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
|
||||
endif
|
||||
|
||||
BL31_SOURCES += ${RK_GIC_SOURCES} \
|
||||
drivers/arm/cci/cci.c \
|
||||
drivers/ti/uart/aarch64/16550_console.S \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/delay_timer/generic_delay_timer.c \
|
||||
drivers/scmi-msg/base.c \
|
||||
drivers/scmi-msg/clock.c \
|
||||
drivers/scmi-msg/entry.c \
|
||||
drivers/scmi-msg/reset_domain.c \
|
||||
drivers/scmi-msg/smt.c \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
lib/cpus/aarch64/cortex_a72.S \
|
||||
$(LIBFDT_SRCS) \
|
||||
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
|
||||
${RK_PLAT_COMMON}/aarch64/platform_common.c \
|
||||
${RK_PLAT_COMMON}/bl31_plat_setup.c \
|
||||
${RK_PLAT_COMMON}/plat_pm.c \
|
||||
${RK_PLAT_COMMON}/plat_pm_helpers.c \
|
||||
${RK_PLAT_COMMON}/plat_topology.c \
|
||||
${RK_PLAT_COMMON}/rockchip_sip_svc.c \
|
||||
${RK_PLAT_COMMON}/params_setup.c \
|
||||
${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S \
|
||||
${RK_PLAT_COMMON}/rockchip_sip_svc.c \
|
||||
${RK_PLAT_COMMON}/scmi/rockchip_common_clock.c \
|
||||
${RK_PLAT_COMMON}/scmi/scmi.c \
|
||||
${RK_PLAT_COMMON}/scmi/scmi_clock.c \
|
||||
${RK_PLAT_COMMON}/scmi/scmi_rstd.c \
|
||||
${RK_PLAT_SOC}/scmi/rk3576_clk.c \
|
||||
${RK_PLAT_SOC}/plat_sip_calls.c \
|
||||
${RK_PLAT_SOC}/drivers/dmc/suspend.c \
|
||||
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
|
||||
${RK_PLAT_SOC}/drivers/pmu/pm_pd_regs.c \
|
||||
${RK_PLAT_SOC}/drivers/secure/firewall.c \
|
||||
${RK_PLAT_SOC}/drivers/secure/secure.c \
|
||||
${RK_PLAT_SOC}/drivers/soc/soc.c
|
||||
|
||||
# Enable workarounds for selected Cortex-A53 errata
|
||||
ERRATA_A53_835769 := 1
|
||||
ERRATA_A53_843419 := 1
|
||||
ERRATA_A53_855873 := 1
|
||||
ERRATA_A53_1530924 := 1
|
||||
|
||||
ERRATA_A72_1319367 := 1
|
||||
|
||||
ENABLE_PLAT_COMPAT := 0
|
||||
MULTI_CONSOLE_API := 1
|
||||
CTX_INCLUDE_EL2_REGS := 0
|
||||
GICV2_G0_FOR_EL3 := 1
|
||||
CTX_INCLUDE_AARCH32_REGS := 0
|
||||
|
||||
# Do not enable SVE
|
||||
ENABLE_SVE_FOR_NS := 0
|
||||
|
||||
WORKAROUND_CVE_2017_5715 := 0
|
||||
|
||||
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
|
||||
207
plat/rockchip/rk3576/rk3576_def.h
Normal file
207
plat/rockchip/rk3576/rk3576_def.h
Normal file
|
|
@ -0,0 +1,207 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_DEF_H__
|
||||
#define __PLAT_DEF_H__
|
||||
|
||||
#define SIZE_K(n) ((n) * 1024)
|
||||
#define SIZE_M(n) ((n) * 1024 * 1024)
|
||||
|
||||
#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits))
|
||||
#define BITS_WMSK(msk, shift) ((msk) << ((shift) + REG_MSK_SHIFT))
|
||||
|
||||
/* Special value used to verify platform parameters from BL2 to BL3-1 */
|
||||
#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
|
||||
|
||||
#define RK3576_DEV_RNG0_BASE 0x00000000
|
||||
#define RK3576_DEV_RNG0_SIZE 0x40000000
|
||||
|
||||
#define RK_DRAM_BASE 0x40000000
|
||||
|
||||
/* All slave base address declare below */
|
||||
#define MCU_TCM_BASE 0x23800000
|
||||
#define MCU_CACHE_BASE 0x23810000
|
||||
#define MCU_RAM_TEST_BASE 0x23820000
|
||||
#define MCU_BOOT_BASE 0x00000000
|
||||
#define MCU_MAIN_BASE 0x00010000
|
||||
#define PMU0SGRF_BASE 0x26000000
|
||||
#define PMU1SGRF_BASE 0x26002000
|
||||
#define PMU1SGRF_FW_BASE 0x26003000
|
||||
#define SYS_SGRF_BASE 0x26004000
|
||||
#define SYS_SGRF_FW_BASE 0x26005000
|
||||
#define SYS_GRF_BASE 0x2600a000
|
||||
#define BIGCORE_GRF_BASE 0x2600c000
|
||||
#define LITCORE_GRF_BASE 0x2600e000
|
||||
#define CCI_GRF_BASE 0x26010000
|
||||
#define DDR_GRF_BASE 0x26012000
|
||||
#define CENTER_GRF_BASE 0x26014000
|
||||
#define GPUGRF_BASE 0x26016000
|
||||
#define NPUGRF_BASE 0x26018000
|
||||
#define VO_GRF_BASE 0x2601a000
|
||||
#define VI_GRF_BASE 0x2601c000
|
||||
#define USB_GRF_BASE 0x2601e000
|
||||
#define PHP_GRF_BASE 0x26020000
|
||||
#define VOP_GRF_BASE 0x26022000
|
||||
#define PMU0_GRF_BASE 0x26024000
|
||||
#define PMU1_GRF_BASE 0x26026000
|
||||
#define USBDPPHY_GRF_BASE 0x2602c000
|
||||
#define USB2PHY0_GRF_BASE 0x2602e000
|
||||
#define USB2PHY1_GRF_BASE 0x26030000
|
||||
#define PMU0_IOC_BASE 0x26040000
|
||||
#define PMU1_IOC_BASE 0x26042000
|
||||
#define TOP_IOC_BASE 0x26044000
|
||||
#define VCCIO_IOC_BASE 0x26046000
|
||||
#define VCCIO6_IOC_BASE 0x2604a000
|
||||
#define VCCIO7_IOC_BASE 0x2604b000
|
||||
#define CRU_BASE 0x27200000
|
||||
#define PHP_CRU_BASE 0x27208000
|
||||
#define SECURE_CRU_BASE 0x27210000
|
||||
#define PMU1_CRU_BASE 0x27220000
|
||||
#define DDRPHY0_CRU_BASE 0x27228000
|
||||
#define DDRPHY1_CRU_BASE 0x27230000
|
||||
#define BIGCORE_CRU_BASE 0x27238000
|
||||
#define LITTLE_CRU_BASE 0x27240000
|
||||
#define CCI_CRU_BASE 0x27248000
|
||||
#define PVTPLL_CCI_BASE 0x27250000
|
||||
#define PVTPLL_BIGCORE_BASE 0x27258000
|
||||
#define PVTPLL_LITCORE_BASE 0x27260000
|
||||
#define PVTPLL_GPU_BASE 0x27268000
|
||||
#define PVTPLL_NPU_BASE 0x27270000
|
||||
#define PVTPLL_CRU_BASE 0x27278000
|
||||
#define I2C0_BASE 0x27300000
|
||||
#define UART1_BASE 0x27310000
|
||||
#define GPIO0_BASE 0x27320000
|
||||
#define PWM0_BASE 0x27330000
|
||||
#define WDT_PMU_BASE 0x27340000
|
||||
#define TIMER_PMU_BASE 0x27350000
|
||||
#define PMU_BASE 0x27360000
|
||||
#define PMU0_BASE 0x27360000
|
||||
#define PMU1_BASE 0x27370000
|
||||
#define PMU2_BASE 0x27380000
|
||||
#define PVTM_PMU_BASE 0x273f0000
|
||||
#define HPTIMER_BASE 0x27400000
|
||||
#define CCI_BASE 0x27500000
|
||||
#define VOP_BASE 0x27d00000
|
||||
#define INTERCONNECT_BASE 0x27f00000
|
||||
#define FW_CCI2DDR_BASE 0x27f80000
|
||||
#define FW_CENTER2DDR_BASE 0x27f90000
|
||||
#define FW_SYSMEM_BASE 0x27fa0000
|
||||
#define FW_VOP2DDR_BASE 0x27fb0000
|
||||
#define FW_CBUF_BASE 0x27fc0000
|
||||
#define FIREWALL_DDR_BASE 0x27f80000
|
||||
#define DDRCTL0_BASE 0x28000000
|
||||
#define DDRCTL1_BASE 0x29000000
|
||||
#define DDR_MONITOR0_BASE 0x2a000000
|
||||
#define DDR_MONITOR1_BASE 0x2a010000
|
||||
#define DDRPHY0_BASE 0x2a020000
|
||||
#define DDRPHY1_BASE 0x2a030000
|
||||
#define HWLP0_BASE 0x2a060000
|
||||
#define HWLP1_BASE 0x2a070000
|
||||
#define KEYLADDER_BASE 0x2a420000
|
||||
#define CRYPTO_S_BASE 0x2a430000
|
||||
#define OTP_S_BASE 0x2a480000
|
||||
#define DCF_BASE 0x2a490000
|
||||
#define STIMER0_BASE 0x2a4a0000
|
||||
#define STIMER1_BASE 0x2a4b0000
|
||||
#define WDT_S_BASE 0x2a4c0000
|
||||
#define OTP_MASK_BASE 0x2a4d0000
|
||||
#define OTP_NS_BASE 0x2a580000
|
||||
#define GIC400_BASE 0x2a700000
|
||||
#define I2C1_BASE 0x2ac40000
|
||||
#define NSTIMER0_BASE 0x2acc0000
|
||||
#define NSTIMER1_BASE 0x2acd0000
|
||||
#define WDT_NS_BASE 0x2ace0000
|
||||
#define UART0_BASE 0x2ad40000
|
||||
#define UART2_BASE 0x2ad50000
|
||||
#define UART3_BASE 0x2ad60000
|
||||
#define UART4_BASE 0x2ad70000
|
||||
#define UART5_BASE 0x2ad80000
|
||||
#define UART6_BASE 0x2ad90000
|
||||
#define UART7_BASE 0x2ada0000
|
||||
#define UART8_BASE 0x2adb0000
|
||||
#define UART9_BASE 0x2adc0000
|
||||
#define PWM1_BASE 0x2add0000
|
||||
#define PWM2_BASE 0x2ade0000
|
||||
#define PWM3_BASE 0x2adf0000
|
||||
#define GPIO1_BASE 0x2ae10000
|
||||
#define GPIO2_BASE 0x2ae20000
|
||||
#define GPIO3_BASE 0x2ae30000
|
||||
#define GPIO4_BASE 0x2ae40000
|
||||
#define TSADC_BASE 0x2ae70000
|
||||
|
||||
#define PMUSRAM_BASE 0x3fe70000
|
||||
#define PMUSRAM_RSIZE SIZE_K(32)
|
||||
|
||||
#define CBUF_BASE 0x3fe80000
|
||||
#define SRAM_BASE 0x3ff80000
|
||||
|
||||
#define STIMER0_CHN_BASE(i) (STIMER0_BASE + 0x1000 * (i))
|
||||
#define STIMER1_CHN_BASE(i) (STIMER1_BASE + 0x1000 * (i))
|
||||
|
||||
#define NSTIMER0_CHN_BASE(i) (NSTIMER0_BASE + 0x1000 * (i))
|
||||
#define NSTIMER1_CHN_BASE(i) (NSTIMER1_BASE + 0x1000 * (i))
|
||||
|
||||
#define DDRPHY_BASE_CH(n) (DDRPHY0_BASE + ((n) * 0x10000))
|
||||
#define DDRPHY_CRU_BASE_CH(n) (DDRPHY0_CRU_BASE + ((n) * 0x8000))
|
||||
#define UMCTL_BASE_CH(n) (DDRCTL0_BASE + ((n) * 0x1000000))
|
||||
#define HWLP_BASE_CH(n) (HWLP0_BASE + ((n) * 0x10000))
|
||||
#define MAILBOX1_BASE (0x2ae50000 + 0xb000)
|
||||
|
||||
#define CRYPTO_S_BY_KEYLAD_BASE CRYPTO_S_BASE
|
||||
|
||||
#define DDR_SHARE_MEM (RK_DRAM_BASE + SIZE_K(1024))
|
||||
#define DDR_SHARE_SIZE SIZE_K(64)
|
||||
|
||||
#define SHARE_MEM_BASE DDR_SHARE_MEM
|
||||
#define SHARE_MEM_PAGE_NUM 15
|
||||
#define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4)
|
||||
|
||||
#define SCMI_SHARE_MEM_BASE (SHARE_MEM_BASE + SHARE_MEM_SIZE)
|
||||
#define SCMI_SHARE_MEM_SIZE SIZE_K(4)
|
||||
|
||||
#define SMT_BUFFER_BASE SCMI_SHARE_MEM_BASE
|
||||
#define SMT_BUFFER0_BASE SMT_BUFFER_BASE
|
||||
|
||||
#define ROCKCHIP_PM_REG_REGION_MEM_SIZE SIZE_K(8)
|
||||
|
||||
/******************************************************************************
|
||||
* sgi, ppi
|
||||
******************************************************************************/
|
||||
#define RK_IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
#define RK_IRQ_SEC_SGI_0 8
|
||||
#define RK_IRQ_SEC_SGI_1 9
|
||||
#define RK_IRQ_SEC_SGI_2 10
|
||||
#define RK_IRQ_SEC_SGI_3 11
|
||||
#define RK_IRQ_SEC_SGI_4 12
|
||||
#define RK_IRQ_SEC_SGI_5 13
|
||||
#define RK_IRQ_SEC_SGI_6 14
|
||||
#define RK_IRQ_SEC_SGI_7 15
|
||||
|
||||
/*
|
||||
* Define a list of Group 0 interrupts.
|
||||
*/
|
||||
#define PLAT_RK_GICV2_G0_IRQS \
|
||||
INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
|
||||
|
||||
/* UART related constants */
|
||||
#define RK_DBG_UART_BASE UART0_BASE
|
||||
#define RK_DBG_UART_BAUDRATE 1500000
|
||||
#define RK_DBG_UART_CLOCK 24000000
|
||||
|
||||
/* Base rk_platform compatible GIC memory map */
|
||||
#define PLAT_GICD_BASE (GIC400_BASE + 0x1000)
|
||||
#define PLAT_GICC_BASE (GIC400_BASE + 0x2000)
|
||||
#define PLAT_GICR_BASE 0
|
||||
|
||||
/* CCI */
|
||||
#define PLAT_RK_CCI_BASE CCI_BASE
|
||||
#define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 1
|
||||
#define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 2
|
||||
|
||||
#endif /* __PLAT_DEF_H__ */
|
||||
1353
plat/rockchip/rk3576/scmi/rk3576_clk.c
Normal file
1353
plat/rockchip/rk3576/scmi/rk3576_clk.c
Normal file
File diff suppressed because it is too large
Load diff
1151
plat/rockchip/rk3576/scmi/rk3576_clk.h
Normal file
1151
plat/rockchip/rk3576/scmi/rk3576_clk.h
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Add table
Reference in a new issue