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https://github.com/ARM-software/arm-trusted-firmware.git
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036935a814
rk3576 is an Octa-core soc with Cortex-a53/a72 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I67a019822bd4af13e4a3cdd09cf06202f4922cc4 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
39 lines
1 KiB
C
39 lines
1 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
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*/
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#include <assert.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <secure.h>
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#include <soc.h>
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static void secure_timer_init(void)
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{
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/* gpu's cntvalue comes from stimer1 channel_5 */
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
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TIMER_DIS);
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_LOAD_COUNT0, 0xffffffff);
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_LOAD_COUNT1, 0xffffffff);
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/* auto reload & enable the timer */
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
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TIMER_EN | TIMER_FMODE);
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}
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void secure_init(void)
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{
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secure_timer_init();
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fw_init();
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/* crypto secure controlled by crypto */
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mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), BITS_WITH_WMASK(0, 0x1, 4));
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mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), BITS_WITH_WMASK(0, 0x1, 5));
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/* disable DP encryption mode */
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mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(1), BITS_WITH_WMASK(1, 0x1, 14));
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}
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