mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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036935a814
rk3576 is an Octa-core soc with Cortex-a53/a72 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I67a019822bd4af13e4a3cdd09cf06202f4922cc4 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
207 lines
6.5 KiB
C
207 lines
6.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
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*/
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#ifndef __PLAT_DEF_H__
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#define __PLAT_DEF_H__
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#define SIZE_K(n) ((n) * 1024)
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#define SIZE_M(n) ((n) * 1024 * 1024)
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#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits))
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#define BITS_WMSK(msk, shift) ((msk) << ((shift) + REG_MSK_SHIFT))
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define RK3576_DEV_RNG0_BASE 0x00000000
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#define RK3576_DEV_RNG0_SIZE 0x40000000
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#define RK_DRAM_BASE 0x40000000
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/* All slave base address declare below */
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#define MCU_TCM_BASE 0x23800000
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#define MCU_CACHE_BASE 0x23810000
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#define MCU_RAM_TEST_BASE 0x23820000
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#define MCU_BOOT_BASE 0x00000000
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#define MCU_MAIN_BASE 0x00010000
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#define PMU0SGRF_BASE 0x26000000
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#define PMU1SGRF_BASE 0x26002000
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#define PMU1SGRF_FW_BASE 0x26003000
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#define SYS_SGRF_BASE 0x26004000
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#define SYS_SGRF_FW_BASE 0x26005000
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#define SYS_GRF_BASE 0x2600a000
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#define BIGCORE_GRF_BASE 0x2600c000
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#define LITCORE_GRF_BASE 0x2600e000
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#define CCI_GRF_BASE 0x26010000
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#define DDR_GRF_BASE 0x26012000
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#define CENTER_GRF_BASE 0x26014000
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#define GPUGRF_BASE 0x26016000
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#define NPUGRF_BASE 0x26018000
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#define VO_GRF_BASE 0x2601a000
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#define VI_GRF_BASE 0x2601c000
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#define USB_GRF_BASE 0x2601e000
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#define PHP_GRF_BASE 0x26020000
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#define VOP_GRF_BASE 0x26022000
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#define PMU0_GRF_BASE 0x26024000
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#define PMU1_GRF_BASE 0x26026000
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#define USBDPPHY_GRF_BASE 0x2602c000
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#define USB2PHY0_GRF_BASE 0x2602e000
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#define USB2PHY1_GRF_BASE 0x26030000
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#define PMU0_IOC_BASE 0x26040000
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#define PMU1_IOC_BASE 0x26042000
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#define TOP_IOC_BASE 0x26044000
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#define VCCIO_IOC_BASE 0x26046000
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#define VCCIO6_IOC_BASE 0x2604a000
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#define VCCIO7_IOC_BASE 0x2604b000
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#define CRU_BASE 0x27200000
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#define PHP_CRU_BASE 0x27208000
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#define SECURE_CRU_BASE 0x27210000
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#define PMU1_CRU_BASE 0x27220000
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#define DDRPHY0_CRU_BASE 0x27228000
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#define DDRPHY1_CRU_BASE 0x27230000
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#define BIGCORE_CRU_BASE 0x27238000
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#define LITTLE_CRU_BASE 0x27240000
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#define CCI_CRU_BASE 0x27248000
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#define PVTPLL_CCI_BASE 0x27250000
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#define PVTPLL_BIGCORE_BASE 0x27258000
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#define PVTPLL_LITCORE_BASE 0x27260000
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#define PVTPLL_GPU_BASE 0x27268000
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#define PVTPLL_NPU_BASE 0x27270000
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#define PVTPLL_CRU_BASE 0x27278000
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#define I2C0_BASE 0x27300000
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#define UART1_BASE 0x27310000
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#define GPIO0_BASE 0x27320000
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#define PWM0_BASE 0x27330000
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#define WDT_PMU_BASE 0x27340000
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#define TIMER_PMU_BASE 0x27350000
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#define PMU_BASE 0x27360000
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#define PMU0_BASE 0x27360000
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#define PMU1_BASE 0x27370000
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#define PMU2_BASE 0x27380000
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#define PVTM_PMU_BASE 0x273f0000
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#define HPTIMER_BASE 0x27400000
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#define CCI_BASE 0x27500000
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#define VOP_BASE 0x27d00000
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#define INTERCONNECT_BASE 0x27f00000
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#define FW_CCI2DDR_BASE 0x27f80000
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#define FW_CENTER2DDR_BASE 0x27f90000
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#define FW_SYSMEM_BASE 0x27fa0000
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#define FW_VOP2DDR_BASE 0x27fb0000
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#define FW_CBUF_BASE 0x27fc0000
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#define FIREWALL_DDR_BASE 0x27f80000
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#define DDRCTL0_BASE 0x28000000
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#define DDRCTL1_BASE 0x29000000
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#define DDR_MONITOR0_BASE 0x2a000000
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#define DDR_MONITOR1_BASE 0x2a010000
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#define DDRPHY0_BASE 0x2a020000
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#define DDRPHY1_BASE 0x2a030000
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#define HWLP0_BASE 0x2a060000
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#define HWLP1_BASE 0x2a070000
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#define KEYLADDER_BASE 0x2a420000
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#define CRYPTO_S_BASE 0x2a430000
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#define OTP_S_BASE 0x2a480000
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#define DCF_BASE 0x2a490000
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#define STIMER0_BASE 0x2a4a0000
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#define STIMER1_BASE 0x2a4b0000
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#define WDT_S_BASE 0x2a4c0000
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#define OTP_MASK_BASE 0x2a4d0000
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#define OTP_NS_BASE 0x2a580000
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#define GIC400_BASE 0x2a700000
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#define I2C1_BASE 0x2ac40000
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#define NSTIMER0_BASE 0x2acc0000
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#define NSTIMER1_BASE 0x2acd0000
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#define WDT_NS_BASE 0x2ace0000
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#define UART0_BASE 0x2ad40000
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#define UART2_BASE 0x2ad50000
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#define UART3_BASE 0x2ad60000
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#define UART4_BASE 0x2ad70000
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#define UART5_BASE 0x2ad80000
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#define UART6_BASE 0x2ad90000
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#define UART7_BASE 0x2ada0000
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#define UART8_BASE 0x2adb0000
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#define UART9_BASE 0x2adc0000
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#define PWM1_BASE 0x2add0000
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#define PWM2_BASE 0x2ade0000
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#define PWM3_BASE 0x2adf0000
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#define GPIO1_BASE 0x2ae10000
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#define GPIO2_BASE 0x2ae20000
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#define GPIO3_BASE 0x2ae30000
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#define GPIO4_BASE 0x2ae40000
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#define TSADC_BASE 0x2ae70000
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#define PMUSRAM_BASE 0x3fe70000
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#define PMUSRAM_RSIZE SIZE_K(32)
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#define CBUF_BASE 0x3fe80000
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#define SRAM_BASE 0x3ff80000
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#define STIMER0_CHN_BASE(i) (STIMER0_BASE + 0x1000 * (i))
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#define STIMER1_CHN_BASE(i) (STIMER1_BASE + 0x1000 * (i))
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#define NSTIMER0_CHN_BASE(i) (NSTIMER0_BASE + 0x1000 * (i))
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#define NSTIMER1_CHN_BASE(i) (NSTIMER1_BASE + 0x1000 * (i))
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#define DDRPHY_BASE_CH(n) (DDRPHY0_BASE + ((n) * 0x10000))
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#define DDRPHY_CRU_BASE_CH(n) (DDRPHY0_CRU_BASE + ((n) * 0x8000))
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#define UMCTL_BASE_CH(n) (DDRCTL0_BASE + ((n) * 0x1000000))
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#define HWLP_BASE_CH(n) (HWLP0_BASE + ((n) * 0x10000))
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#define MAILBOX1_BASE (0x2ae50000 + 0xb000)
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#define CRYPTO_S_BY_KEYLAD_BASE CRYPTO_S_BASE
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#define DDR_SHARE_MEM (RK_DRAM_BASE + SIZE_K(1024))
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#define DDR_SHARE_SIZE SIZE_K(64)
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#define SHARE_MEM_BASE DDR_SHARE_MEM
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#define SHARE_MEM_PAGE_NUM 15
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#define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4)
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#define SCMI_SHARE_MEM_BASE (SHARE_MEM_BASE + SHARE_MEM_SIZE)
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#define SCMI_SHARE_MEM_SIZE SIZE_K(4)
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#define SMT_BUFFER_BASE SCMI_SHARE_MEM_BASE
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#define SMT_BUFFER0_BASE SMT_BUFFER_BASE
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#define ROCKCHIP_PM_REG_REGION_MEM_SIZE SIZE_K(8)
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/******************************************************************************
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* sgi, ppi
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******************************************************************************/
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#define RK_IRQ_SEC_PHY_TIMER 29
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#define RK_IRQ_SEC_SGI_0 8
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#define RK_IRQ_SEC_SGI_1 9
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#define RK_IRQ_SEC_SGI_2 10
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#define RK_IRQ_SEC_SGI_3 11
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#define RK_IRQ_SEC_SGI_4 12
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#define RK_IRQ_SEC_SGI_5 13
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#define RK_IRQ_SEC_SGI_6 14
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#define RK_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 0 interrupts.
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*/
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#define PLAT_RK_GICV2_G0_IRQS \
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INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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/* UART related constants */
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#define RK_DBG_UART_BASE UART0_BASE
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#define RK_DBG_UART_BAUDRATE 1500000
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#define RK_DBG_UART_CLOCK 24000000
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/* Base rk_platform compatible GIC memory map */
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#define PLAT_GICD_BASE (GIC400_BASE + 0x1000)
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#define PLAT_GICC_BASE (GIC400_BASE + 0x2000)
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#define PLAT_GICR_BASE 0
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/* CCI */
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#define PLAT_RK_CCI_BASE CCI_BASE
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#define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 1
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#define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 2
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#endif /* __PLAT_DEF_H__ */
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