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https://github.com/ARM-software/arm-trusted-firmware.git
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036935a814
rk3576 is an Octa-core soc with Cortex-a53/a72 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I67a019822bd4af13e4a3cdd09cf06202f4922cc4 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
129 lines
3.3 KiB
C
129 lines
3.3 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
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*/
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#include <assert.h>
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#include <errno.h>
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#include <arch_helpers.h>
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#include <bl31/bl31.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_compat.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <pmu.h>
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#include <plat_private.h>
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#include <rk3576_clk.h>
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#include <secure.h>
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#include <soc.h>
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const mmap_region_t plat_rk_mmap[] = {
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MAP_REGION_FLAT(RK3576_DEV_RNG0_BASE, RK3576_DEV_RNG0_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_SHARE_MEM, DDR_SHARE_SIZE,
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MT_DEVICE | MT_RW | MT_NS),
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{ 0 }
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};
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/* The RockChip power domain tree descriptor */
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const unsigned char rockchip_power_domain_tree_desc[] = {
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/* No of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* No of children for the root node */
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PLATFORM_CLUSTER_COUNT,
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/* No of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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/* No of children for the second cluster node */
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PLATFORM_CLUSTER1_CORE_COUNT
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};
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static void clear_glb_reset_status(void)
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{
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uint32_t cru_sel55 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(55));
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/* switch pclk_bus_root to 24M before writing CRU_GLB_RST_ST */
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mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(55),
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BITS_WITH_WMASK(2, 0x3, 2));
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dsb();
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mmio_write_32(CRU_BASE + CRU_GLB_RST_ST, 0xffff);
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dsb();
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mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(55),
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WITH_16BITS_WMSK(cru_sel55));
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}
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static void print_glb_reset_status(void)
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{
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uint32_t glb_rst_st = 0, warm_boot = 0;
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/* clear CRU_GLB_RST_ST_NCLR if cold boot */
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if (mmio_read_32(PMU0_GRF_BASE + PMU0GRF_OS_REG(17)) == WARM_BOOT_MAGIC) {
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/* ignore npu_wdt*/
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glb_rst_st = mmio_read_32(CRU_BASE + CRU_GLB_RST_ST_NCLR) & VALID_GLB_RST_MSK;
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warm_boot = 1;
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} else {
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mmio_write_32(PMU0_GRF_BASE + PMU0GRF_OS_REG(17), WARM_BOOT_MAGIC);
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}
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clear_glb_reset_status();
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/* save glb_rst_st in mem_os_reg31 */
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write_mem_os_reg(31, glb_rst_st);
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if (warm_boot != 0)
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INFO("soc warm boot, reset status: 0x%x\n", glb_rst_st);
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else
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INFO("soc cold boot\n");
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}
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static void system_reset_init(void)
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{
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/*
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* enable tsadc trigger global reset and select first reset.
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* enable global reset and wdt trigger pmu reset.
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* select first reset trigger pmu reset.
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*/
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mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 0xffdf);
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/* enable wdt_s reset */
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mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), 0x20002000);
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/* enable wdt_ns reset */
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mmio_write_32(SYS_GRF_BASE + SYSGRF_SOC_CON(4), 0x01000100);
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/* reset width = 0xffff */
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mmio_write_32(PMU1_GRF_BASE + PMU1GRF_SOC_CON(6), 0xffffffff);
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/* enable first/tsadc/wdt reset output */
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mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(0), 0x00070007);
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/* pmu0sgrf pmu0_ioc hold */
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mmio_write_32(PMU0SGRF_BASE + PMU1SGRF_SOC_CON(0), 0xffff1800);
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/* pmu1sgrf pmu1_grf hold */
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mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(16), 0xffff8800);
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/* select tsadc_shut_m0 ionmux*/
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mmio_write_32(PMU0_IOC_BASE + 0x0, 0x00f00090);
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print_glb_reset_status();
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}
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void plat_rockchip_soc_init(void)
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{
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rockchip_clock_init();
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system_reset_init();
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secure_init();
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rockchip_init_scmi_server();
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/* release cpu1~cpu7 */
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mmio_write_32(CCI_GRF_BASE + CCIGRF_CON(4), 0xffffffff);
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mmio_write_32(LITCORE_GRF_BASE + COREGRF_CPU_CON(1),
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BITS_WITH_WMASK(0x77, 0xff, 4));
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}
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