mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-18 02:24:18 +00:00
036935a814
rk3576 is an Octa-core soc with Cortex-a53/a72 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I67a019822bd4af13e4a3cdd09cf06202f4922cc4 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
271 lines
7.5 KiB
C
271 lines
7.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2025, Rockchip Electronics Co., Ltd.
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*/
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#ifndef __SOC_H__
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#define __SOC_H__
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enum pll_id {
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APLL_ID,
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CPLL_ID,
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DPLL_ID,
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GPLL_ID,
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};
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enum cru_mode_con00 {
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CLK_APLL,
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CLK_CPLL,
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CLK_GPLL,
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CLK_DPLL,
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};
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#define KHz 1000
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#define MHz (1000 * KHz)
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#define OSC_HZ (24 * MHz)
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#define MCU_VALID_START_ADDRESS 0x800000
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/* CRU */
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#define GLB_SRST_FST_CFG_VAL 0xfdb9
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#define CRU_PLLS_CON(pll_id, i) ((pll_id) * 0x20 + (i) * 0x4)
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#define CRU_PLL_CON(i) ((i) * 0x4)
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#define CRU_MODE_CON 0x280
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#define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
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#define CRU_CLKSEL_CON_CNT 181
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#define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
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#define CRU_CLKGATE_CON_CNT 80
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#define CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
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#define CRU_SOFTRST_CON_CNT 80
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#define CRU_GLB_CNT_TH 0xc00
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#define CRU_GLB_RST_ST 0xc04
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#define CRU_GLB_SRST_FST 0xc08
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#define CRU_GLB_SRST_SND 0xc0c
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#define CRU_GLB_RST_CON 0xc10
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#define CRU_GLB_RST_ST_NCLR 0xc14
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#define CRU_LITCOREWFI_CON0 0xc40
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#define CRU_BIGCOREWFI_CON0 0xc44
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#define CRU_NON_SECURE_GT_CON0 0xc48
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#define CRU_PLLCON0_M_MASK 0x3ff
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#define CRU_PLLCON0_M_SHIFT 0
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#define CRU_PLLCON1_P_MASK 0x3f
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#define CRU_PLLCON1_P_SHIFT 0
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#define CRU_PLLCON1_S_MASK 0x7
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#define CRU_PLLCON1_S_SHIFT 6
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#define CRU_PLLCON2_K_MASK 0xffff
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#define CRU_PLLCON2_K_SHIFT 0
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#define CRU_PLLCON1_PWRDOWN BIT(13)
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#define CRU_PLLCON6_LOCK_STATUS BIT(15)
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/* LCORE_CRU */
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#define LCORE_CRU_MODE_CON 0x280
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#define LCORE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
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#define LCORE_CRU_CLKSEL_CON_CNT 4
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#define LCORE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
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#define LCORE_CRU_CLKGATE_CON_CNT 2
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#define LCORE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
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#define LCORE_CRU_SOFTRST_CON_CNT 4
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/* BCORE_CRU */
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#define BCORE_CRU_MODE_CON 0x280
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#define BCORE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
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#define BCORE_CRU_CLKSEL_CON_CNT 5
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#define BCORE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
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#define BCORE_CRU_CLKGATE_CON_CNT 3
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#define BCORE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
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#define BCORE_CRU_SOFTRST_CON_CNT 4
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/* DDRCRU */
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#define DDRCRU_MODE_CON 0x280
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#define DDRCRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
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#define DDRCRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
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#define DDRCRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
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/* CCICRU */
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#define CCICRU_MODE_CON 0x280
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#define CCICRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
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#define CCICRU_CLKSEL_CON_CNT 10
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#define CCICRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
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#define CCICRU_CLKGATE_CON_CNT 7
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#define CCICRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
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#define CCICRU_SOFTRST_CON_CNT 7
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/* CRU AUTOCS */
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#define CRU_AUTOCS_CON(offset) (CRU_BASE + (offset))
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#define CRU_AUTOCS_SEC_CON(offset) (SECURE_CRU_BASE + (offset))
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#define CRU_AUTOCS_CCI_CON(offset) (CCI_CRU_BASE + (offset))
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#define AUTOCS_EN_BIT BIT(12)
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/* PHP_CRU */
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#define PHP_CRU_MODE_CON 0x280
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#define PHP_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
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#define PHP_CRU_CLKSEL_CON_CNT 2
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#define PHP_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
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#define PHP_CRU_CLKGATE_CON_CNT 2
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#define PHP_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
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#define PHP_CRU_SOFTRST_CON_CNT 2
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/* SECURE CRU */
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#define SECURE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
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#define SECURE_CRU_CLKSEL_CON_CNT 1
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#define SECURE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
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#define SECURE_CRU_CLKGATE_CON_CNT 1
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#define SECURE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
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#define SECURE_CRU_SOFTRST_CON_CNT 1
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/* SECURE SCRU */
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#define SECURE_SCRU_CLKSEL_CON(i) ((i) * 0x4 + 0x4000)
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#define SECURE_SCRU_CLKSEL_CON_CNT 7
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#define SECURE_SCRU_CLKGATE_CON(i) ((i) * 0x4 + 0x4028)
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#define SECURE_SCRU_CLKGATE_CON_CNT 6
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#define SECURE_SCRU_SOFTRST_CON(i) ((i) * 0x4 + 0x4050)
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#define SECURE_SCRU_SOFTRST_CON_CNT 6
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#define SECURE_SCRU_MODE_CON 0x4280
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/* SYSGRF */
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#define SYSGRF_SOC_CON(i) ((i) * 4)
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#define SYSGRF_SOC_STATUS 0x30
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#define SYSGRF_NOC_CON(i) (0x40 + (i) * 4)
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#define SYSGRF_NOC_STATUS(i) (0x60 + (i) * 4)
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#define SYSGRF_MEM_CON(i) (0x80 + (i) * 4)
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#define SYSGRF_STATUS0 0x140
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#define SYSGRF_STATUS1 0x144
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/* COREGRF */
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#define COREGRF_SOC_STATUS(i) (0x2c + (i) * 4)
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#define COREGRF_CPU_CON(i) (0x34 + (i) * 4)
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/* DDRGRF */
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#define DDRGRF_CHA_CON(i) ((i) * 4)
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#define DDRGRF_CHB_CON(i) (0x100 + (i) * 4)
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#define DDRGRF_CHA_ST(i) (0x60 + (i) * 4)
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#define DDRGRF_CHB_ST(i) (0xb0 + (i) * 4)
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#define DDRGRF_CON(i) (0x140 + (i) * 4)
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/* CCIGRF */
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#define CCIGRF_CON(i) ((i) * 4)
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#define CCIGRF_STATUS(i) (0x34 + (i) * 4)
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/* IOC */
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#define VCCIO_IOC_MISC_CON(i) (0x400 + (i) * 4)
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/* pvtm */
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#define PVTM_CON(i) (0x4 + (i) * 4)
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#define PVTM_INTEN 0x70
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#define PVTM_INTSTS 0x74
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#define PVTM_STATUS(i) (0x80 + (i) * 4)
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#define PVTM_CALC_CNT 0x200
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enum pvtm_con0 {
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pvtm_start = 0,
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pvtm_osc_en = 1,
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pvtm_osc_sel = 2,
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pvtm_rnd_seed_en = 5,
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};
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/* WDT */
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#define WDT_CR 0x0
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#define WDT_TORR 0x4
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#define WDT_CCVR 0x8
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#define WDT_CRR 0xc
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#define WDT_STAT 0x10
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#define WDT_EOI 0x14
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#define WDT_EN BIT(0)
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#define WDT_RSP_MODE BIT(1)
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/* timer */
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#define TIMER_LOAD_COUNT0 0x00
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#define TIMER_LOAD_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0c
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_INTSTATUS 0x18
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#define TIMER_DIS 0x0
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#define TIMER_EN 0x1
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#define TIMER_FMODE (0x0 << 1)
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#define TIMER_RMODE (0x1 << 1)
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/* hp timer */
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#define TIMER_HP_REVISION 0x00
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#define TIMER_HP_CTRL 0x04
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#define TIMER_HP_INTR_EN 0x08
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#define TIMER_HP_T24_GCD 0x0c
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#define TIMER_HP_T32_GCD 0x10
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#define TIMER_HP_LOAD_COUNT0 0x14
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#define TIMER_HP_LOAD_COUNT1 0x18
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#define TIMER_HP_T24_DELAT_COUNT0 0x1c
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#define TIMER_HP_T24_DELAT_COUNT1 0x20
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#define TIMER_HP_CURR_32K_VALUE0 0x24
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#define TIMER_HP_CURR_32K_VALUE1 0x28
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#define TIMER_HP_CURR_TIMER_VALUE0 0x2c
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#define TIMER_HP_CURR_TIMER_VALUE1 0x30
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#define TIMER_HP_T24_32BEGIN0 0x34
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#define TIMER_HP_T24_32BEGIN1 0x38
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#define TIMER_HP_T32_24END0 0x3c
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#define TIMER_HP_T32_24END1 0x40
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#define TIMER_HP_BEGIN_END_VALID 0x44
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#define TIMER_HP_SYNC_REQ 0x48
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#define TIMER_HP_INTR_STATUS 0x4c
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#define TIMER_HP_UPD_EN 0x50
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/* GPIO */
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#define GPIO_SWPORT_DR_L 0x0000
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#define GPIO_SWPORT_DR_H 0x0004
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#define GPIO_SWPORT_DDR_L 0x0008
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#define GPIO_SWPORT_DDR_H 0x000c
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#define GPIO_INT_EN_L 0x0010
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#define GPIO_INT_EN_H 0x0014
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#define GPIO_INT_MASK_L 0x0018
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#define GPIO_INT_MASK_H 0x001c
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#define GPIO_INT_TYPE_L 0x0020
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#define GPIO_INT_TYPE_H 0x0024
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#define GPIO_INT_POLARITY_L 0x0028
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#define GPIO_INT_POLARITY_H 0x002c
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#define GPIO_INT_BOTHEDGE_L 0x0030
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#define GPIO_INT_BOTHEDGE_H 0x0034
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#define GPIO_DEBOUNCE_L 0x0038
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#define GPIO_DEBOUNCE_H 0x003c
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#define GPIO_DBCLK_DIV_EN_L 0x0040
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#define GPIO_DBCLK_DIV_EN_H 0x0044
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#define GPIO_DBCLK_DIV_CON 0x0048
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#define GPIO_INT_STATUS 0x0050
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#define GPIO_INT_RAWSTATUS 0x0058
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#define GPIO_PORT_EOI_L 0x0060
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#define GPIO_PORT_EOI_H 0x0064
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#define GPIO_EXT_PORT 0x0070
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#define GPIO_VER_ID 0x0078
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#define GPIO_STORE_ST_L 0x0080
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#define GPIO_STORE_ST_H 0x0084
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#define GPIO_REG_GROUP_L 0x0100
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#define GPIO_REG_GROUP_H 0x0104
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#define GPIO_VIRTUAL_EN 0x0108
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#define GPIO_REG_GROUP1_L 0x0110
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#define GPIO_REG_GROUP1_H 0x0114
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#define GPIO_REG_GROUP2_L 0x0118
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#define GPIO_REG_GROUP2_H 0x011c
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#define GPIO_REG_GROUP3_L 0x0120
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#define GPIO_REG_GROUP3_H 0x0124
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/* PWM */
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#define PMW_PWRCAPTURE_VAL 0x15c
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#define SOC_RK3576A1 0x35760101
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#define SOC_RK3576J1 0x35760a01
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#define SOC_RK3576M1 0x35760d01
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#define SOC_RK3576S1 0x35761301
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#define SOC_UNKNOWN 0xeeee
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#define SOC_ROOT 0x0
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int rk_soc_is_(uint32_t soc_id);
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uint32_t timer_hp_get_freq(void);
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int soc_bus_div_sip_handler(uint32_t id, uint32_t cfg, uint32_t enable_msk);
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void autocs_suspend(void);
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void autocs_resume(void);
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#endif /* __SOC_H__ */
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