the TPM functionality. Since it deviates from our normal TIS compliant
TPMs it can't be started twice since running the selftests twice hangs.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEgWII69YpahbL5iK5gS8AYozs+qIFAmf9acgACgkQgS8AYozs
+qL43hAAqf+35bIE4V6K3WTNZiuPMbd2rZFs1O7/14fZ8nuWQls9w0GJAFaXf9ts
wFfGKzNCegZjc/YwOZFrOLkSZRsB66xHI5eqfjnXMfCErpy+hhJgX6LYIyNKhtk8
T9pqr48g8MEGrvYYOeJFWFFxEdMy2R+jTpLehxdWHz/HzMWxHg+OGkAHE8YlUDMY
YAxaprtxWNIRfuMUgGpjz9dAFTXGWYM3Y2qaQMNUAbIoNMRaRgtB1UWFvYkYRBKV
fjzWCTInBWBWL41hDGp0UewAvOqoAoogUJZEcqqkgzEaddtQS4cQnIACg4efZ8En
7vNYO/vAnUrAsVIrNa8TGwCTe5hsLxI2/1pj0D2ic5nNF7+K84C/LGqnTnXZ1JO6
DyHIZhl9OGDHQX65KRQV6S1V3DPsHN/OD5RSzuLta+1fH0QvK+ThB3nNCRxvdJyZ
P/R+l+dun+VlvBTmpPM0BusjVUYjMpmGmJ7HLUIecLsNYZgqbFRer9FMIgVTzwsE
4SkMLsOf1y0Xwl/LLNdLr8kxZrZ+RCkC5yCyj/dH6opS4EgsqWYvaeu5SDH/saRD
808tAEQJu9dSgyicqr5CN2uikzNboArR0ykCQz0bGX3Lo4zOAjzFMPHeEU2FhHFC
0R0wx//6ngofJ1ABEHcQ7dGUOiCA4RmWoxg3f4ETWMWxPQtKW+U=
=kqde
-----END PGP SIGNATURE-----
Merge tag 'tpm-master-14042025' of https://source.denx.de/u-boot/custodians/u-boot-tpm
A small fix for the cr50 which is a TPM but doesn't support all
the TPM functionality. Since it deviates from our normal TIS compliant
TPMs it can't be started twice since running the selftests twice hangs.
When FIT image with multiple dtbs are involved for R5 boot process,
R5 SPL starts off with the first instance of dtb to probe the
eeprom, then once we have identified the type of board, invocation
of setup_multi_dtb_fit will replace the gd->fdt_blob with the proper
board dtb match. However, when we do this, two things happen:
a) Prior to the invocation of setup_multi_dtb_fit, as part of the eeprom
discovery process, i2c controller device is already probed and marked
as exclusive with the match of the very first tisci match (from the
original boot dtb). This list is stored in the info->dev_list of the
first probe.
b) When the second dtb is loaded, tisci is probed again (since this is a
new node) and the new info->dev_list is empty.
At this stage, the exclusive devices such as i2c instances used to
probe the board information is left in the old info->dev_list that is
no longer used actively by the system using the replaced dtb.
As a result of this, the cleanup we intend to do with
ti_sci_cmd_release_exclusive_devices is no longer complete and
leaves the instances such as i2c for eeprom marked used as we scan just
the new info->dev_list.
This creates a problem when Device Manager(DM) firmware starts up later
on in the boot process and identifies that this instance of i2c is
already marked active, so it assumes this can no longer be controlled
by software and is marked internally as reserved and HLOS can no
longer control these instances. This defeated the purpose of
ti_sci_cmd_release_exclusive_devices.
NOTE: This scheme works just fine if the FIT has just a single dtb as
the info->dev_list is upto date.
To fix this, let us make ti_sci_cmd_release_exclusive_devices scan the
all registrations of tisci instances and cleanup all exclusive devices
that have ever been registered.
As part of this, change the prototype of release_exclusive_devices to
drop the handle since that has no further meaning now.
Though this issue was identified on AM64-sk, this can be present in
other builds which use multi-fit-dtb for R5 SPL startup.
Fixes: 9566b777ae ("firmware: ti_sci: Add a command for releasing all exclusive devices")
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
iomux_match_device() returns -ENOENT instead of the end index, which means
console_stop() is never called at the moment for unused consoles.
This prevents e.g. f_acm from releasing the USB gadget interface when
removing it from stdio/stderr/stdin.
Fixes: b672c1619b ("IOMUX: Split out iomux_match_device() helper")
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The tpm_auto_start() function is used in tests and assumes that it can
open the TPM even if it is already open and a locality claimed. The cr50
driver does not use the common TPM2 TIS code so lacks a check for the
is_open field of struct tpm_chip and in fact it doesn't use that struct.
Add an equivalent check to cr50_i2c_open().
This fixes all init sequences on that TPM -- e.g 'tpm init && tpm init'
or 'tpm autostart && tpm init' used to hang
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jerome Forissier <jerome.forissier@linaro.org> says:
This series replaces the dynamic initcalls (with function pointers) with
static calls, and gets rid of initcall_run_list(), init_sequence_f,
init_sequence_f_r and init_sequence_r. This makes the code simpler and the
binary slighlty smaller: -2281 bytes/-0.21 % with LTO enabled and -510
bytes/-0.05 % with LTO disabled (xilinx_zynqmp_kria_defconfig).
Execution time doesn't seem to change noticeably. There is no impact on
the SPL.
The inline assembly fixes, although they look unrelated, are triggered
on some platforms with LTO enabled. For example: kirkwood_defconfig.
CI: https://source.denx.de/u-boot/custodians/u-boot-net/-/pipelines/25514
Link: https://lore.kernel.org/r/20250404135038.2134570-1-jerome.forissier@linaro.org
Change board_init_f(), board_init_f_r() and board_init_r() to make
static calls instead of iterating over the init_sequence_f,
init_sequence_f_r and init_sequence_r arrays, respectively. This makes
the code a simpler (and even more so when initcall_run_list() is
later removed) and it reduces the binary size as well. Tested with
xilinx_zynqmp_kria_defconfig; bloat-o-meter results:
- With LTO
add/remove: 106/196 grow/shrink: 10/28 up/down: 31548/-33829 (-2281)
Total: Before=1070471, After=1068190, chg -0.21%
- Without LTO
add/remove: 0/54 grow/shrink: 3/0 up/down: 2322/-2832 (-510)
Total: Before=1121723, After=1121213, chg -0.05%
Execution time does not change in a noticeable way.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
The mcr and msr instructions are available in Thumb mode only if
Thumb2 is supported. Therefore, if __thumb2__ is not set, make
sure we switch to ARM mode by inserting a .arm directive in the
inline assembly.
Fixes LTO link errors with kirkwood platforms, triggered by a later
commit:
tools/buildman/buildman -o /tmp/build -eP sheevaplug
[...]
{standard input}:24085: Error: selected processor does not support `mrc p15,0,r3,c1,c0,0' in Thumb mode
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tom reports that generating the ESL file we need for authenticated
capsule updates fails to work on azure which expects a RO git tree.
Move it to $(objtree)
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
UART-A can be exposed through uSD, this was tested on Transformer T20
but should work on all Ventana-based boards.
TX is exported on SDD pingroup corresponding to uSD CLK pin
RX is exported on SDB which is CMD pin in uSD slot
Signed-off-by: Artur Kowalski <arturkow2000@gmail.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The Tegra Note 7 is a mini tablet computer and the second Tegra 4
based mobile device designed by Nvidia that runs the Android operating
system. The Tegra Note has a 7" IPS display with 1280 x 800 (217 ppi)
resolution. The 1 GB of RAM and 16 GB of internal memory can be
supplemented with a microSDXC card giving up to 64 GB of additional
storage.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The ASUS Transformer Pad TF701T is an Android tablet computer made by
ASUS, successor to the ASUS Transformer Pad Infinity. The tablet includes
a Tegra 4 T114 processor clocked at 1.9 GHz, and an upgraded 2560×1600
pixel resolution screen, increasing the pixel density to 300 PPI and
a mobile dock. Transformers (t114) board derives from Nvidia Macallan
development board.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The clock initialization routine sets the DISP* clock parent to PLLC,
resulting in DC failure in the case when PLLD was previously configured.
This issue disrupts chainloading and to prevent failures caused by DISP*
clock parent conflicts, clock initialization should not modify DISP*. The
DC driver handles DISP* configuration.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Most device headers contain SoC specific part and common Tegra post part.
Add a generic header which can be used by any Tegra device of one of the
supported SoC generations (T20, T30, T114, T124 or T210) without need in
device specific configuration.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Link CFG_SYS_NS16550_COM1 value to chosen CONFIG_TEGRA_ENABLE_UART Tegra
wide. Remove all CFG_SYS_NS16550_COM1 from device headers.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Applies same logic to general Tegra pincontrol driver as is done to Tegra20
by commit:
a35bf832d7 ("pinctrl: tegra20: detect unknown/invalid pin/func
configurations")
Suggested-by: Artur Kowalski <arturkow2000@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Tegra20 driver doesn't know about some pin configurations and even about
some pins. In case when pin configuration is unknown the pin would be
muxed to whatever is under function 0, in case when pin itself is
unknown, it could cause out-of-bounds array access in pinmux_set_func
and pinmux_set_pullupdown.
Signed-off-by: Artur Kowalski <arturkow2000@gmail.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The Motorola Atrix 4G (MB860) and Droid X2 (MB870) both featured a
dual-core NVIDIA Tegra 2 AP20H processor clocked at 1GHz, coupled with 1GB
of DDR2 RAM. Storage consisted of 16GB of internal flash memory, expandable
via microSD. The display was a 4.0-inch TFT LCD with a resolution of
960x540 pixels (qHD). The devices originally ran on Android up to 2.3
(Gingerbread).
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The LM3532 is a 500-kHz fixed frequency asynchronous boost converter which
provides the power for 3 high-voltage, low-side current sinks. The device
is programmable over an I2C-compatible interface and has independent
current control for all three channels.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Add support for the LCD panel module used in Motorola Atrix 4G or Droid X2.
Exact panel vendor and model are unknown. The panel has a 540x960 (qHD)
resolution and uses 24 bit RGB per pixel.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
CPCAP has a dedicated interrupt for power button. Implement this to have
more input control over the devices.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC whose
main purpose was power control. It was used in a wide variety of Motorola
products, both Tegra and OMAP based. The most notable devices using this
PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Place Tegra124 SOR and eDP implenetation into common Tegra driver folder
until it is integrated into existing setup.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Since this set of drivers suports four Tegra SoC generations, lets name it
just 'tegra'.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
GPIO reset and power-off functionality depends on device tree data, which
is often absent in SPL or TPL. To address this, incorporate PHASE_ into the
config option and add Kconfig option or each phase.
Adjust SYSRESET_GPIO and POWEROFF_GPIO uses to address possible
regressions.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Historically, PLLD2 mirrored PLLD's layout on Tegra30 and 114. However,
with the introduction of Tegra124, this changed. This layout alteration was
not considered, and it now requires a corrective action to prevent future
complications.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
PLLD and PLLD2 clocks possess a unique enable bit within their
miscellaneous register. Take this into account when using clock_set_rate
function.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Add missing configuration of chip select polarity. Default polarity is LOW,
which satisfies most cases but some devices require HIGH polarity and will
not work.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Simon Glass <sjg@chromium.org> says:
This series adds a cover-coverage check to CI for Binman. The iMX8 tests
are still not completed, so a work-around is included for those.
A few fixes are included for some other problems.
Link: https://lore.kernel.org/r/20250410124333.843527-1-sjg@chromium.org
Binman includes a good set of tests covering all of its functionality.
This includes a code-coverage test.
However to date the code-coverage test has not been checked
automatically by CI, relying on people to run 'binman test -T'
themselves.
Plug the gap to avoid bugs creeping in future.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Newer lz4 util is not happy with any padding at end of file,
it would abort with error message like:
Stream followed by undecodable data at position 43.
Workaround by skipping testCompUtilPadding test case and manually
strip padding in testCompressSectionSize test case.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
The CheckAddHashValue() function is always called before this one, so
the algorithm check is never used. Replace it with an assert to avoid a
coverage error.
Signed-off-by: Simon Glass <sjg@chromium.org>
Newer versions of the python3-coverage tool require a directory
separator before and after the directory name. Add this so that system
package are not included in the coverage report.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini <trini@konsulko.com> says:
This series switches to always using $(PHASE_) in Makefiles when
building rather than $(PHASE_) or $(XPL_). It also starts on documenting
this part of the build, but as a follow-up we need to rename
doc/develop/spl.rst and expand on explaining things a bit.
Link: https://lore.kernel.org/r/20250401225851.1125678-1-trini@konsulko.com
Expand the conditional compilation section to explain when to use
CONFIG_IS_ENABLED rather than IS_ENABLED and provide an example. Next,
note what the PHASE_ macro is supposed to be used for as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
In order to make a start on explaining how and when to use certain
macros, we need to document their usage somewhere. As a first step, take
section 21 of the v6.13 Linux Kernel coding-style document on
conditional compilation, verbatim, and add it to our documentation.
Further rewording to be clearer about U-Boot will be done next.
Signed-off-by: Tom Rini <trini@konsulko.com>
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.
Signed-off-by: Tom Rini <trini@konsulko.com>
When the `optee hello' subcommand is called, the do_optee_hello_world_ta()
function passes a NULL pointer to the strcmp() function while verifying its
input argument, which results in the following crash:
=> optee hello
"Synchronous Abort" handler, esr 0x96000010, far 0x0
Fix this by verifying the number of input arguments instead.
Fixes: e3cf80fbe0 ("cmd: Add support for optee commands")
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jerome Forissier <jerome.forissier@linaro.org>
Cc: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
The number of memory banks in QEMU is not bounded by 1.
In this example we have two banks:
qemu-system-aarch64 \
-machine virt \
-nographic \
-cpu cortex-a72 \
-m 8G \
-smp 8,sockets=2,cores=4,threads=1 \
-object memory-backend-ram,id=mem0,size=4G \
-numa node,cpus=0-3,memdev=mem0 \
-object memory-backend-ram,id=mem1,size=4G \
-numa node,cpus=4-7,memdev=mem1 \
-bios u-boot.bin
Use the default value defined in /Kconfig as 4.
Suggested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Suggested-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The AM62x uses the DA8XX (DaVinci) GPIO controller. Enable
CONFIG_DA8XX_GPIO to support GPIO access from the Cortex-A53.
Also enable the 'gpio' command to allow users to interact
with GPIOs from the U-Boot shell.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
