board: nvidia: tegratab: add Nvidia Tegra Note 7 support

The Tegra Note 7 is a mini tablet computer and the second Tegra 4
based mobile device designed by Nvidia that runs the Android operating
system. The Tegra Note has a 7" IPS display with 1280 x 800 (217 ppi)
resolution. The 1 GB of RAM and 16 GB of internal memory can be
supplemented with a microSDXC card giving up to 64 GB of additional
storage.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This commit is contained in:
Svyatoslav Ryhel 2023-06-29 10:10:26 +03:00
parent 00d4996a82
commit b12931d7de
14 changed files with 1381 additions and 0 deletions

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@ -120,6 +120,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
tegra30-wexler-qc750.dtb \
tegra114-asus-tf701t.dtb \
tegra114-dalmore.dtb \
tegra114-nvidia-tegratab.dtb \
tegra124-apalis.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \

File diff suppressed because it is too large Load diff

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@ -8,6 +8,10 @@ config TARGET_DALMORE
bool "NVIDIA Tegra114 Dalmore evaluation board"
select BOARD_LATE_INIT
config TARGET_TEGRATAB
bool "NVIDIA Tegra114 TegraTab evaluation board"
select BOARD_LATE_INIT
config TARGET_TRANSFORMER_T114
bool "ASUS Tegra114 Transformer board"
select BOARD_LATE_INIT
@ -18,6 +22,7 @@ config SYS_SOC
default "tegra114"
source "board/nvidia/dalmore/Kconfig"
source "board/nvidia/tegratab/Kconfig"
source "board/asus/transformer-t114/Kconfig"
endif

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@ -0,0 +1,16 @@
if TARGET_TEGRATAB
config SYS_BOARD
default "tegratab"
config SYS_VENDOR
default "nvidia"
config SYS_CONFIG_NAME
default "tegratab"
config TEGRA_BOARD_STRING
string "Default Tegra board name"
default "NVIDIA TegraTab"
endif

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@ -0,0 +1,8 @@
TEGRATAB BOARD
M: Svyatoslav Ryhel <clamor95@gmail.com>
S: Maintained
F: arch/arm/dts/tegra114-nvidia-tegratab.dts
F: board/nvidia/tegratab/
F: configs/tegratab_defconfig
F: doc/board/nvidia/tegratab.rst
F: include/configs/tegratab.h

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@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0
#
# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
#
# Copyright (c) 2023, Svyatoslav Ryhel <clamor95@gmail.com>
#
obj-$(CONFIG_XPL_BUILD) += tegratab-spl.o
obj-y += tegratab.o

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@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* TegraTab SPL stage configuration
*
* (C) Copyright 2010-2013
* NVIDIA Corporation <www.nvidia.com>
*
* (C) Copyright 2023
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
#define TPS65913_I2C_ADDR (0x58 << 1)
#define TPS65913_SMPS12_CTRL 0x20
#define TPS65913_SMPS12_VOLTAGE 0x23
#define TPS65913_SMPS45_CTRL 0x28
#define TPS65913_SMPS45_VOLTAGE 0x2B
#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL)
#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE)
#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL)
#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE)
void pmic_enable_cpu_vdd(void)
{
/* Set CORE VDD to 1.200V. */
tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA);
udelay(1000);
tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA);
udelay(1000);
/* Set CPU VDD to 1.0125V. */
tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA);
udelay(1000);
tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA);
udelay(10 * 1000);
}

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@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010-2013
* NVIDIA Corporation <www.nvidia.com>
*
* (C) Copyright 2023
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <dm.h>
#include <fdt_support.h>
#include <i2c.h>
#include <log.h>
#ifdef CONFIG_MMC_SDHCI_TEGRA
#define TPS65913_I2C_ADDRESS 0x58
#define TPS65913_PRIMARY_SECONDARY_PAD2 0xfb
#define GPIO_4 BIT(0)
#define TPS65913_PRIMARY_SECONDARY_PAD3 0xfe
#define DVFS2 BIT(1)
#define DVFS1 BIT(0)
/* We are using this function only till palmas pinctrl driver is available */
void pin_mux_mmc(void)
{
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(0, TPS65913_I2C_ADDRESS, 1, &dev);
if (ret) {
log_debug("%s: cannot find PMIC I2C chip\n", __func__);
return;
}
/* GPIO4 function has to be GPIO */
dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD2,
GPIO_4, 0);
/* DVFS1 is enabled, DVFS2 is disabled */
dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD3,
DVFS2 | DVFS1, DVFS1);
}
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
/* Remove TrustZone nodes and memory reserves */
fdt_del_node_and_alias(blob, "/firmware");
fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
fdt_del_node_and_alias(blob, "/reserved-memory/bootloader-firmware@b7e00000");
return 0;
}
#endif

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@ -0,0 +1,15 @@
button_cmd_0_name=Volume Down
button_cmd_0=bootmenu
button_cmd_1_name=Hall Sensor
button_cmd_1=poweroff
fastboot_partition_alias_boot=CAC
fastboot_partition_alias_root=UDA
bootmenu_0=mount internal storage=usb start && ums 0 mmc 0:c; bootmenu
bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
bootmenu_3=reboot RCM=enterrcm
bootmenu_4=reboot=reset
bootmenu_5=power off=poweroff
bootmenu_delay=-1

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@ -0,0 +1,84 @@
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SUPPORT_PASSING_ATAGS=y
CONFIG_CMDLINE_TAG=y
CONFIG_INITRD_TAG=y
CONFIG_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SOURCE_FILE="tegratab"
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0xFFFFD000
CONFIG_DEFAULT_DEVICE_TREE="tegra114-nvidia-tegratab"
CONFIG_SPL_STACK=0x800ffffc
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_TEGRA114=y
CONFIG_TARGET_TEGRATAB=y
CONFIG_TEGRA_ENABLE_UARTD=y
CONFIG_BUTTON_CMD=y
CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_KEYED_CTRLC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
CONFIG_SYS_PBSIZE=2086
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra114 (TegraTab) # "
# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_TEGRA_PARTITION=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_BUTTON=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x91000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_PALMAS_GPIO=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET_PALMAS=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
CONFIG_VIDEO_LCD_LG_LD070WX3=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_DSI_TEGRA=y

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@ -42,6 +42,7 @@ Board-specific doc
microchip/index
microsoft/index
motorola/index
nvidia/index
nxp/index
openpiton/index
ouya/index

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@ -0,0 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0+
NVIDIA
======
.. toctree::
:maxdepth: 2
tegratab

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@ -0,0 +1,74 @@
.. SPDX-License-Identifier: GPL-2.0+
U-Boot for the Nvidia Tegra Note 7
==================================
Quick Start
-----------
- Build U-Boot
- Boot U-Boot by loading it into RAM (coldboot)
- Chainloading U-Boot from the vendor bootloader
- Boot
Build U-Boot
------------
U-Boot can be built in two forms: U-Boot with SPL, which is used for booting
by loading directly into RAM and U-Boot without SPL, which can be flashed
and chainloaded from the vendor bootloader.
To build U-Boot with SPL proseed:
.. code-block:: bash
$ export CROSS_COMPILE=arm-none-eabi-
$ make tegratab_defconfig
$ make
After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
file, ready for cold booting by loading into RAM.
To build U-Boot without SPL adjust tegratab_defconfig:
.. code-block::
CONFIG_TEXT_BASE=0x80A00000
CONFIG_SKIP_LOWLEVEL_INIT=y
# CONFIG_OF_BOARD_SETUP is not set
CONFIG_TEGRA_SUPPORT_NON_SECURE=y
After the build succeeds, you will obtain the final ``u-boot-dtb.bin`` file,
ready for booting with fastboot boot or which can be further processed into
a flashable boot.img.
Boot U-Boot by loading it into RAM (coldboot)
---------------------------------------------
Done fairly simply by using fusee-tools (using run_bootloader.sh) and placing
``u-boot-dtb-tegra.bin`` generated on the previous step into fusee-tools dir.
This method requires constant access to the host PC or payloader and can fully
eliminate influence of the vendor bootloader onto the boot process.
.. code-block:: bash
$ ./run_bootloader.sh -s T114 -t ./bct/tegratab.bct
Chainloading U-Boot from the vendor bootloader
----------------------------------------------
``u-boot-dtb.bin`` has to be further packed into Android boot image form,
where ``u-boot-dtb.bin`` acts as kernel, while dtb and ramdisk parts should
not be included. Then the generated boot image can be flashed into the /boot
partition of the tablet using vendor bootloader's fastboot and will act as
the bootloader of the last stage.
Boot
----
In both cases after U-Boot obtains control it performs search of extlinux.conf
first on the dock USB device is available, then on MicroSD card if available
and lastly on eMMC. If none of the devices above are present, then the device
is turned off.
If during boot of U-Boot Volume Down button is pressed, the device will enter
U-Boot bootmenu.

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@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
* Copyright (c) 2023, Svyatoslav Ryhel <clamor95@gmail.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "tegra114-common.h"
#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE
#define CFG_PRAM 0x21c00 /* 135 MB */
#endif
#include "tegra-common-post.h"
#endif /* __CONFIG_H */