It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.
Signed-off-by: Tom Rini <trini@konsulko.com>
This adds support for the ADP588 GPIO expander from Analog Devices. It
is accessed over I2C and provides up to 18 pins. It is largely a port of
the Linux driver developed by Michael Hennerich
<michael.hennerich@analog.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
Signed-off-by: Greg Malysa <malysagreg@gmail.com>
Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com>
Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com>
Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
This adds support for using the GPIO pins on the SC5XX family of SoCs
from Analog Devices.
Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Co-developed-by: Ian Roberts <ian.roberts@timesys.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com>
Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com>
Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com>
Signed-off-by: Greg Malysa <malysagreg@gmail.com>
The Aspeed SGPIO driver supports the SGPIO controllers found in the
AST2400, AST2500 and AST2600 BMC SoCs. The implementation is a cut-down
copy of the upstream Linux kernel driver, adapted for u-boot.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Simon Glass <sjg@chromium.org> says:
When the SPL build-phase was first created it was designed to solve a
particular problem (the need to init SDRAM so that U-Boot proper could
be loaded). It has since expanded to become an important part of U-Boot,
with three phases now present: TPL, VPL and SPL
Due to this history, the term 'SPL' is used to mean both a particular
phase (the one before U-Boot proper) and all the non-proper phases.
This has become confusing.
For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL'
phases, not just SPL. So code which can only be compiled for actual SPL,
for example, must use something like this:
#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
In Makefiles we have similar issues. SPL_ has been used as a variable
which expands to either SPL_ or nothing, to chose between options like
CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable
was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was
updated to support 'VPL_' as well.
This series starts a change in terminology and usage to resolve the
above issues:
- The word 'xPL' is used instead of 'SPL' to mean a non-proper build
- A new CONFIG_XPL_BUILD define indicates that the current build is an
'xPL' build
- The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now
defined for TPL and VPL phases
- The existing SPL_ Makefile variable is renamed to SPL_
- The existing SPL_TPL Makefile variable is renamed to PHASE_
It should be noted that xpl_phase() can generally be used instead of
the above CONFIGs without a code-space or run-time penalty.
This series does not attempt to convert all of U-Boot to use this new
terminology but it makes a start. In particular, renaming spl.h and
common/spl seems like a bridge too far at this point.
The series is fully bisectable. It has also been checked to ensure there
are no code-size changes on any commit.
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.
Update the comment in bootstage to refer to this symbol, instead of
SPL_
Signed-off-by: Simon Glass <sjg@chromium.org>
So we can disable to build ADP5585 in SPL to save size
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
In the 7th generation of the SoC from Aspeed, the control logic of the
GPIO controller has been updated to support per-pin control. Each pin now
has its own 32-bit register, allowing for individual control of the pin’s
value, direction, interrupt type, and other settings.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Add Nuvoton BMC NPCM7xx/NPCM8xx sgpio driver.
BMC can use this driver to increase 64 GPI pins and 64 GPO pins to use.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Add support for system power off via UCLASS_SYSRESET. Newer versions of
Turris Omnia MCU firmware can power off the board (MCU will disable
almost all voltage regulators and go into low power mode).
Move the MCU driver into drivers/misc and register it under UCLASS_MISC.
The sysreset and gpio device are bound as child devices of the MCU device.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
MAXIM Semiconductor's PMIC, MAX77663 has 8 GPIO pins and 3 GPIO-like
pins. It also supports interrupts from these pins.
Add GPIO driver for these pins to control via GPIO APIs.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This driver adds support for the gpio features of the GPIO/PFC module in
the Renesas RZ/G2L (R9A07G044) SoC.
The new `rzg2l-pfc-gpio` driver is bound to the same device tree node as
the `rzg2l-pfc-pinctrl` driver as the same hardware block provides both
GPIO and pin multiplexing features.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The mpc832x has GPIOs handled by the QUICC Engine.
The registers are different from the one for the
non QE mpc83xx GPIOs.
Implement a GPIO driver for those.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
- A fix for a long standing bug that has been exposed by commit
50128aeb0f ("cyclic: get rid of cyclic_init()") preventing 8xx boards
from booting since u-boot 2023.01
- A GPIO driver for powerpc 8xx chip
- Fixup for powerpc 8xx SPI driver
- A new powerpc 8xx board
- The two devices having that board.
Ports A, C and D are 16 bits ports.
Ports B and E are 32 bits ports.
The "compatible" is used to determine each port type.
This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
This is not used since this commit:
7458f18e5c ppc: Remove MPC8313ERDB boards
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
The KONA and KONA_GPIO options don't exist anymore, since this commit:
0f6807e77b arm: Remove bcm28155_ap board
Drop the dead code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add gpio driver for ADP5585 I/O Expander Controller. The ADP5585 is a 10
input/output port expander and can be used to increase the number of
I/Os available to a processor.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Since both pm8916.c and pm8916_gpio.c are already supporting multiple
Qcom SoCs, it makes sense to rename these drivers to pmic_qcom.c and
qcom_pmic_gpio.c respectively. Also, these driver can be extended to
support additional functionality if required for other Qcom SoCs.
Along with this import latest DT binding: qcom,spmi-pmic.txt from Linux
kernel and thereby remove pm8916.txt.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
The last user of this driver was removed in commit dee08b1999 ("arm:
Remove gplugd board"). Remove the unused driver.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Pali Rohár <pali@kernel.org>
This driver registers GPIO controller and allows U-Boot to control GPIO
pins on MCU which is connected to Turris Omnia via i2c.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
microblaze:
- Add support for reserved memory
xilinx:
- Update FRU code with MAC reading
zynqmp:
- Remove double AMS setting
- DT updates (mostly for SOMs)
- Add support for zcu106 rev 1.0
zynq:
- Update nand binding
nand:
- Aligned zynq_nand to upstream DT binding
net:
- Add support for ethernet-phy-id
mmc:
- Workaround CD in zynq_sdhci driver also for ZynqMP
- Add support for dynamic/run-time SD config for SOMs
gpio:
- Add driver for slg7xl45106
firmware:
- Add support for dynamic SD config
power-domain:
- Update zynqmp driver with the latest firmware
video:
- Add skeleton driver for DP and DPDMA
i2c:
- Fix i2c to work with QEMU
pinctrl:
- Add driver for zynqmp pinctrl driver
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Merge tag 'xilinx-for-v2022.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2022.07-rc1
microblaze:
- Add support for reserved memory
xilinx:
- Update FRU code with MAC reading
zynqmp:
- Remove double AMS setting
- DT updates (mostly for SOMs)
- Add support for zcu106 rev 1.0
zynq:
- Update nand binding
nand:
- Aligned zynq_nand to upstream DT binding
net:
- Add support for ethernet-phy-id
mmc:
- Workaround CD in zynq_sdhci driver also for ZynqMP
- Add support for dynamic/run-time SD config for SOMs
gpio:
- Add driver for slg7xl45106
firmware:
- Add support for dynamic SD config
power-domain:
- Update zynqmp driver with the latest firmware
video:
- Add skeleton driver for DP and DPDMA
i2c:
- Fix i2c to work with QEMU
pinctrl:
- Add driver for zynqmp pinctrl driver
The Aspeed GPIO driver supports the GPIO controllers found in the
AST2400, AST2500 and AST2600 BMC SoCs. The implementation is a cut-down
copy of the upstream Linux kernel driver, adapted for u-boot.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
slg7xl45106 is i2c based 8-bit gpo expander, gpo pins are set and get by
writing and reading corresponding gpo bit value into its data register.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/839f475cc75c97ffb3496a4caa93de2faabdbca2.1645629688.git.michal.simek@xilinx.com
The gpio block is part of the sl28cpld sl28cpld management controller.
There are three different flavors: the usual input and output where the
direction is configurable, but also input only and output only variants.
Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Initial support for Fairchild's 8 bit I2C gpio expander FXL6408.
The CONFIG_FXL6408_GPIO define enables support for such devices.
Based on: https://patchwork.kernel.org/patch/9148419/
Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
ZynqMP modepin driver has capability to get/set/check status of modepin
gpios. These modepins are accessed using xilinx firmware. In modepin
register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits
set/clear IO.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com
This board has not been converted to CONFIG_DM by the deadline.
Remove it. As this is the last armada100 platform, remove that support
as well.
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add support for accessing GPIOs using of-plata. This uses the same
mechanism as for clocks, but allows use of the xlate() method so that
the driver can interpret the parameters.
Update the condition for GPIO_HOG so that it is not built into SPL,
since it needs SPL_OF_REAL which is not enabled in sandbox_spl.
Signed-off-by: Simon Glass <sjg@chromium.org>
Introduce driver for I2C based MCP230xx GPIO chips, which are
quite common and already well supported by the Linux kernel.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Nomadik GPIO is a fairly simple GPIO module used in the ST-Ericsson
Ux500 SoCs (and some older Nomadik SoCs). It uses registers where
each GPIO is represented as a single bit, plus "set" and "clear"
registers that allow updating the state without having to read the
existing state.
The driver implements support for it for use together with DM_GPIO
and the existing ste-dbx5x0.dtsi device tree.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
The original U-Boot port for the ST-Ericsson U8500 SoC was dropped
in commit 68282f55b8 ("arm: Remove unused ST-Ericsson u8500 arch").
Most of the drivers related to the old port were removed, but the
db8500_gpio.c driver was forgotten for some reason. There is no way
to select it and it does not compile anymore because of missing
headers, so let's just remove it.
The new port for U8500 introduced in commit 689088f9da
("arm: Add support for ST-Ericsson U8500 SoC") fully embraces the
new Driver Model and device trees where possible, so this is
preparation to add a new, simplified GPIO driver based on DM_GPIO.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them. As this is
the last of the SPEAr platforms, so remove the rest of the remaining
support as well.
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add support for GPIO controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- livetree API (dev_read_...) is used instead of fdt one (fdt...).
Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi
chip select, SPISEL_BOOT, that is used by the boot code to boot from
flash.
This chip select will typically be used to select a SPI boot
flash. The SPISEL_BOOT signal is controlled by a single bit in the
SPI_CS register.
Implement a gpio driver for the spi chip select register. This allows a
spi driver capable of using gpios as chip select, to bind a chip select
to SPISEL_BOOT.
It may be a little odd to do this as a GPIO driver, since the signal
is neither GP or I, but it is quite convenient to present it to the
spi driver that way. The alternative it to teach mpc8xxx_spi to handle
the SPISEL_BOOT signal itself (that is how it's done in the linux
kernel, see commit 69b921acae8a)
Signed-off-by: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Since commit bcee8d6764 ("dm: gpio: Allow control of GPIO uclass in SPL")
CONFIG_DM_74X164 is no longer built for mx7dsabresd_defconfig, as
this target does not use CONFIG_SPL_GPIO.
Remove such dependency and let the the 74X164 GPIO driver be built
again.
This restores Ethernet functionality on the imx7-sdb board as the
Ethernet reset PHY comes from a GPIO driven by a 74LV595PW I/O
expander.
Fixes: bcee8d6764 ("dm: gpio: Allow control of GPIO uclass in SPL")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Alifer Moraes <alifer.wsdm@gmail.com>
