mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-04 12:04:17 +00:00
Merge patch series "Tidy up use of 'SPL' and CONFIG_SPL_BUILD"
Simon Glass <sjg@chromium.org> says: When the SPL build-phase was first created it was designed to solve a particular problem (the need to init SDRAM so that U-Boot proper could be loaded). It has since expanded to become an important part of U-Boot, with three phases now present: TPL, VPL and SPL Due to this history, the term 'SPL' is used to mean both a particular phase (the one before U-Boot proper) and all the non-proper phases. This has become confusing. For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL' phases, not just SPL. So code which can only be compiled for actual SPL, for example, must use something like this: #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) In Makefiles we have similar issues. SPL_ has been used as a variable which expands to either SPL_ or nothing, to chose between options like CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was updated to support 'VPL_' as well. This series starts a change in terminology and usage to resolve the above issues: - The word 'xPL' is used instead of 'SPL' to mean a non-proper build - A new CONFIG_XPL_BUILD define indicates that the current build is an 'xPL' build - The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now defined for TPL and VPL phases - The existing SPL_ Makefile variable is renamed to SPL_ - The existing SPL_TPL Makefile variable is renamed to PHASE_ It should be noted that xpl_phase() can generally be used instead of the above CONFIGs without a code-space or run-time penalty. This series does not attempt to convert all of U-Boot to use this new terminology but it makes a start. In particular, renaming spl.h and common/spl seems like a bridge too far at this point. The series is fully bisectable. It has also been checked to ensure there are no code-size changes on any commit.
This commit is contained in:
Tom Rini
commit
47e544f576
906 changed files with 2270 additions and 2237 deletions
14
Makefile
14
Makefile
|
|
@ -624,7 +624,7 @@ include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
|
|||
@# Otherwise, 'make silentoldconfig' would be invoked twice.
|
||||
$(Q)touch include/config/auto.conf
|
||||
|
||||
u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg:
|
||||
u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg vpl/u-boot.cfg:
|
||||
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf $(@)
|
||||
|
||||
-include include/autoconf.mk
|
||||
|
|
@ -829,7 +829,7 @@ KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
|
|||
UBOOTINCLUDE := \
|
||||
-Iinclude \
|
||||
$(if $(KBUILD_SRC), -I$(srctree)/include) \
|
||||
$(if $(CONFIG_$(SPL_)SYS_THUMB_BUILD), \
|
||||
$(if $(CONFIG_$(XPL_)SYS_THUMB_BUILD), \
|
||||
$(if $(CONFIG_HAS_THUMB2), \
|
||||
$(if $(CONFIG_CPU_V7M), \
|
||||
-I$(srctree)/arch/arm/thumb1/include), \
|
||||
|
|
@ -864,7 +864,7 @@ libs-y += disk/
|
|||
libs-y += drivers/
|
||||
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
|
||||
libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
|
||||
libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/
|
||||
libs-$(CONFIG_$(XPL_)ALTERA_SDRAM) += drivers/ddr/altera/
|
||||
libs-y += drivers/usb/cdns3/
|
||||
libs-y += drivers/usb/dwc3/
|
||||
libs-y += drivers/usb/common/
|
||||
|
|
@ -883,7 +883,7 @@ libs-y += drivers/usb/ulpi/
|
|||
ifdef CONFIG_POST
|
||||
libs-y += post/
|
||||
endif
|
||||
libs-$(CONFIG_$(SPL_TPL_)UNIT_TEST) += test/
|
||||
libs-$(CONFIG_$(PHASE_)UNIT_TEST) += test/
|
||||
libs-$(CONFIG_UT_ENV) += test/env/
|
||||
libs-$(CONFIG_UT_OPTEE) += test/optee/
|
||||
libs-$(CONFIG_UT_OVERLAY) += test/overlay/
|
||||
|
|
@ -2104,7 +2104,7 @@ spl/u-boot-spl-dtb.hex: spl/u-boot-spl
|
|||
@:
|
||||
|
||||
spl/u-boot-spl: tools prepare $(if $(CONFIG_SPL_OF_CONTROL),dts/dt.dtb)
|
||||
$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
|
||||
$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.xpl all
|
||||
|
||||
spl/sunxi-spl.bin: spl/u-boot-spl
|
||||
@:
|
||||
|
|
@ -2123,14 +2123,14 @@ tpl/u-boot-tpl.bin: tpl/u-boot-tpl
|
|||
$(TPL_SIZE_CHECK)
|
||||
|
||||
tpl/u-boot-tpl: tools prepare $(if $(CONFIG_TPL_OF_CONTROL),dts/dt.dtb)
|
||||
$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
|
||||
$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.xpl all
|
||||
|
||||
vpl/u-boot-vpl.bin: vpl/u-boot-vpl
|
||||
@:
|
||||
$(VPL_SIZE_CHECK)
|
||||
|
||||
vpl/u-boot-vpl: tools prepare $(if $(CONFIG_TPL_OF_CONTROL),dts/dt.dtb)
|
||||
$(Q)$(MAKE) obj=vpl -f $(srctree)/scripts/Makefile.spl all
|
||||
$(Q)$(MAKE) obj=vpl -f $(srctree)/scripts/Makefile.xpl all
|
||||
|
||||
TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
|
||||
|
||||
|
|
|
|||
100
README
100
README
|
|
@ -133,96 +133,6 @@ run some of U-Boot's tests.
|
|||
|
||||
See doc/arch/sandbox/sandbox.rst for more details.
|
||||
|
||||
|
||||
Board Initialisation Flow:
|
||||
--------------------------
|
||||
|
||||
This is the intended start-up flow for boards. This should apply for both
|
||||
SPL and U-Boot proper (i.e. they both follow the same rules).
|
||||
|
||||
Note: "SPL" stands for "Secondary Program Loader," which is explained in
|
||||
more detail later in this file.
|
||||
|
||||
At present, SPL mostly uses a separate code path, but the function names
|
||||
and roles of each function are the same. Some boards or architectures
|
||||
may not conform to this. At least most ARM boards which use
|
||||
CONFIG_SPL_FRAMEWORK conform to this.
|
||||
|
||||
Execution typically starts with an architecture-specific (and possibly
|
||||
CPU-specific) start.S file, such as:
|
||||
|
||||
- arch/arm/cpu/armv7/start.S
|
||||
- arch/powerpc/cpu/mpc83xx/start.S
|
||||
- arch/mips/cpu/start.S
|
||||
|
||||
and so on. From there, three functions are called; the purpose and
|
||||
limitations of each of these functions are described below.
|
||||
|
||||
lowlevel_init():
|
||||
- purpose: essential init to permit execution to reach board_init_f()
|
||||
- no global_data or BSS
|
||||
- there is no stack (ARMv7 may have one but it will soon be removed)
|
||||
- must not set up SDRAM or use console
|
||||
- must only do the bare minimum to allow execution to continue to
|
||||
board_init_f()
|
||||
- this is almost never needed
|
||||
- return normally from this function
|
||||
|
||||
board_init_f():
|
||||
- purpose: set up the machine ready for running board_init_r():
|
||||
i.e. SDRAM and serial UART
|
||||
- global_data is available
|
||||
- stack is in SRAM
|
||||
- BSS is not available, so you cannot use global/static variables,
|
||||
only stack variables and global_data
|
||||
|
||||
Non-SPL-specific notes:
|
||||
- dram_init() is called to set up DRAM. If already done in SPL this
|
||||
can do nothing
|
||||
|
||||
SPL-specific notes:
|
||||
- you can override the entire board_init_f() function with your own
|
||||
version as needed.
|
||||
- preloader_console_init() can be called here in extremis
|
||||
- should set up SDRAM, and anything needed to make the UART work
|
||||
- there is no need to clear BSS, it will be done by crt0.S
|
||||
- for specific scenarios on certain architectures an early BSS *can*
|
||||
be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing
|
||||
of BSS prior to entering board_init_f()) but doing so is discouraged.
|
||||
Instead it is strongly recommended to architect any code changes
|
||||
or additions such to not depend on the availability of BSS during
|
||||
board_init_f() as indicated in other sections of this README to
|
||||
maintain compatibility and consistency across the entire code base.
|
||||
- must return normally from this function (don't call board_init_r()
|
||||
directly)
|
||||
|
||||
Here the BSS is cleared. For SPL, if CONFIG_SPL_STACK_R is defined, then at
|
||||
this point the stack and global_data are relocated to below
|
||||
CONFIG_SPL_STACK_R_ADDR. For non-SPL, U-Boot is relocated to run at the top of
|
||||
memory.
|
||||
|
||||
board_init_r():
|
||||
- purpose: main execution, common code
|
||||
- global_data is available
|
||||
- SDRAM is available
|
||||
- BSS is available, all static/global variables can be used
|
||||
- execution eventually continues to main_loop()
|
||||
|
||||
Non-SPL-specific notes:
|
||||
- U-Boot is relocated to the top of memory and is now running from
|
||||
there.
|
||||
|
||||
SPL-specific notes:
|
||||
- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
|
||||
CONFIG_SYS_FSL_HAS_CCI400
|
||||
|
||||
Defined For SoC that has cache coherent interconnect
|
||||
CCN-400
|
||||
|
||||
CONFIG_SYS_FSL_HAS_CCN504
|
||||
|
||||
Defined for SoC that has cache coherent interconnect CCN-504
|
||||
|
||||
The following options need to be configured:
|
||||
|
||||
- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX.
|
||||
|
|
@ -1508,13 +1418,13 @@ Low Level (hardware related) configuration options:
|
|||
This only takes effect if the memory commands are activated
|
||||
globally (CONFIG_CMD_MEMORY).
|
||||
|
||||
- CONFIG_SPL_BUILD
|
||||
- CONFIG_XPL_BUILD
|
||||
Set when the currently running compilation is for an artifact
|
||||
that will end up in one of the 'xPL' builds, i.e. SPL, TPL or
|
||||
VPL. Code that needs phase-specific behaviour can check this,
|
||||
or (where possible) use spl_phase() instead.
|
||||
or (where possible) use xpl_phase() instead.
|
||||
|
||||
Note that CONFIG_SPL_BUILD *is* always defined when either
|
||||
Note that CONFIG_XPL_BUILD *is* always defined when either
|
||||
of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be
|
||||
counter-intuitive and should perhaps be changed.
|
||||
|
||||
|
|
@ -1522,13 +1432,13 @@ Low Level (hardware related) configuration options:
|
|||
Set when the currently running compilation is for an artifact
|
||||
that will end up in the TPL build (as opposed to SPL, VPL or
|
||||
U-Boot proper). Code that needs phase-specific behaviour can
|
||||
check this, or (where possible) use spl_phase() instead.
|
||||
check this, or (where possible) use xpl_phase() instead.
|
||||
|
||||
- CONFIG_VPL_BUILD
|
||||
Set when the currently running compilation is for an artifact
|
||||
that will end up in the VPL build (as opposed to the SPL, TPL
|
||||
or U-Boot proper). Code that needs phase-specific behaviour can
|
||||
check this, or (where possible) use spl_phase() instead.
|
||||
check this, or (where possible) use xpl_phase() instead.
|
||||
|
||||
- CONFIG_ARCH_MAP_SYSMEM
|
||||
Generally U-Boot (and in particular the md command) uses
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
|
||||
ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
|
||||
CONFIG_CPU_V7A=
|
||||
CONFIG_CPU_ARM720T=y
|
||||
endif
|
||||
|
|
@ -24,7 +24,7 @@ endif
|
|||
|
||||
# On Tegra systems we must build SPL for the armv4 core on the device
|
||||
# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
|
||||
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
|
||||
ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
|
||||
arch-y += -D__LINUX_ARM_ARCH__=4
|
||||
else
|
||||
arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
|
||||
|
|
@ -106,7 +106,7 @@ libs-y += $(machdirs)
|
|||
|
||||
head-y := arch/arm/cpu/$(CPU)/start.o
|
||||
|
||||
ifeq ($(CONFIG_SPL_BUILD),y)
|
||||
ifeq ($(CONFIG_XPL_BUILD),y)
|
||||
ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs")
|
||||
head-y := arch/arm/cpu/arm926ejs/mxs/start.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm
|
|||
endif
|
||||
|
||||
# Choose between ARM/Thumb instruction sets
|
||||
ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
|
||||
ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y)
|
||||
AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always)
|
||||
PF_CPPFLAGS_ARM := $(AFLAGS_IMPLICIT_IT) \
|
||||
$(call cc-option, -mthumb -mthumb-interwork,\
|
||||
|
|
@ -53,7 +53,7 @@ PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \
|
|||
endif
|
||||
|
||||
# Only test once
|
||||
ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
|
||||
ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y)
|
||||
archprepare: checkthumb checkgcc6
|
||||
|
||||
checkthumb:
|
||||
|
|
@ -99,7 +99,7 @@ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARM) $(PF_CPPFLAGS_ABI)
|
|||
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
|
||||
# This file is parsed many times, so the string may get added multiple
|
||||
# times. Also, the prefix needs to be different based on whether
|
||||
# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry
|
||||
# CONFIG_XPL_BUILD is defined or not. 'filter-out' the existing entry
|
||||
# before adding the correct one.
|
||||
PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \
|
||||
$(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
|
||||
|
|
@ -116,7 +116,7 @@ LDFLAGS_u-boot += -pie
|
|||
#
|
||||
# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
|
||||
#
|
||||
ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
|
||||
ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y)
|
||||
ifeq ($(GAS_BUG_12532),)
|
||||
export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
|
||||
then echo y; else echo n; fi)
|
||||
|
|
@ -126,7 +126,7 @@ PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
|
|||
endif
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ifneq ($(CONFIG_XPL_BUILD),y)
|
||||
# Check that only R_ARM_RELATIVE relocations are generated.
|
||||
INPUTS-y += checkarmreloc
|
||||
# The movt / movw can hardcode 16 bit parts of the addresses in the
|
||||
|
|
@ -160,7 +160,7 @@ endif
|
|||
ifdef CONFIG_MACH_IMX
|
||||
ifneq ($(CONFIG_IMX_CONFIG),"")
|
||||
ifdef CONFIG_SPL
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
ifndef CONFIG_XPL_BUILD
|
||||
INPUTS-y += SPL
|
||||
endif
|
||||
else
|
||||
|
|
|
|||
|
|
@ -5,6 +5,6 @@
|
|||
|
||||
obj-y = cpu.o
|
||||
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ifneq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-$(CONFIG_EFI_LOADER) += sctlr.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ cpu_init_crit:
|
|||
* When booting from NAND - it has definitely been a reset, so, no need
|
||||
* to flush caches and disable the MMU
|
||||
*/
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
/*
|
||||
* flush v4 I/D caches
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -9,6 +9,6 @@ obj-y += cpu.o
|
|||
|
||||
# some files can only build in ARM mode
|
||||
|
||||
ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
|
||||
ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
|
||||
CFLAGS_cpu.o := -marm
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
extra-y = start.o
|
||||
obj-y = cpu.o cache.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_XPL_BUILD
|
||||
ifdef CONFIG_SPL_NO_CPU_SUPPORT
|
||||
extra-y :=
|
||||
endif
|
||||
|
|
@ -17,7 +17,7 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
|||
|
||||
# some files can only build in ARM or THUMB2, not THUMB1
|
||||
|
||||
ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
|
||||
ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
|
||||
ifndef CONFIG_HAS_THUMB2
|
||||
|
||||
CFLAGS_cpu.o := -marm
|
||||
|
|
|
|||
|
|
@ -3,11 +3,11 @@
|
|||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
||||
extra-$(CONFIG_SPL_BUILD) := start.o
|
||||
extra-$(CONFIG_XPL_BUILD) := start.o
|
||||
|
||||
obj-y = clock.o mxs.o iomux.o timer.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_XPL_BUILD
|
||||
obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# Build a combined spl + u-boot image
|
||||
ifdef CONFIG_SPL
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
ifndef CONFIG_XPL_BUILD
|
||||
ALL-y += u-boot-sunxi-with-spl.bin
|
||||
endif
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,12 +12,12 @@ obj-y += syslib.o
|
|||
|
||||
obj-$(CONFIG_SYS_ARM_MPU) += mpu_v7r.o
|
||||
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ifneq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-$(CONFIG_EFI_LOADER) += sctlr.o
|
||||
obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y)
|
||||
ifneq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),y)
|
||||
obj-y += lowlevel_init.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ int cleanup_before_linux_select(int flags)
|
|||
*
|
||||
* we turn off caches etc ...
|
||||
*/
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
disable_interrupts();
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ WEAK(lowlevel_init)
|
|||
/*
|
||||
* Setup a temporary stack. Global data is not available yet.
|
||||
*/
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
|
||||
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
|
||||
ldr sp, =CONFIG_SPL_STACK
|
||||
#else
|
||||
ldr sp, =SYS_INIT_SP_ADDR
|
||||
|
|
@ -39,7 +39,7 @@ WEAK(lowlevel_init)
|
|||
* Set up global data for boards that still need it. This will be
|
||||
* removed soon.
|
||||
*/
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
ldr r9, =gdata
|
||||
#else
|
||||
sub sp, sp, #GD_SIZE
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ ifdef CONFIG_ARCH_NEXELL
|
|||
obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o
|
||||
else
|
||||
obj-y += cpu_info.o
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
ifndef CONFIG_XPL_BUILD
|
||||
obj-y += timer.o
|
||||
obj-y += sromc.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -279,7 +279,7 @@ ENTRY(cpu_init_cp15)
|
|||
orr r2, r4, r2 @ r2 has combined CPU variant + revision
|
||||
|
||||
/* Early stack for ERRATA that needs into call C code */
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
|
||||
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
|
||||
ldr r0, =(CONFIG_SPL_STACK)
|
||||
#else
|
||||
ldr r0, =(SYS_INIT_SP_ADDR)
|
||||
|
|
|
|||
|
|
@ -12,10 +12,10 @@ obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o
|
|||
obj-$(CONFIG_MACH_SUN6I) += sram.o
|
||||
obj-$(CONFIG_MACH_SUN8I) += sram.o
|
||||
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
ifndef CONFIG_XPL_BUILD
|
||||
obj-$(CONFIG_ARMV7_PSCI) += psci.o
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_XPL_BUILD
|
||||
obj-y += fel_utils.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -6,14 +6,14 @@
|
|||
extra-y := start.o
|
||||
|
||||
obj-y += cpu.o
|
||||
ifndef CONFIG_$(SPL_TPL_)TIMER
|
||||
ifndef CONFIG_$(PHASE_)TIMER
|
||||
obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
|
||||
endif
|
||||
ifndef CONFIG_$(SPL_)SYS_DCACHE_OFF
|
||||
ifndef CONFIG_$(XPL_)SYS_DCACHE_OFF
|
||||
obj-y += cache_v8.o
|
||||
obj-y += cache.o
|
||||
endif
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_XPL_BUILD
|
||||
obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o
|
||||
else
|
||||
obj-y += exceptions.o
|
||||
|
|
@ -27,14 +27,14 @@ endif
|
|||
obj-y += cpu-dt.o
|
||||
obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
|
||||
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
ifndef CONFIG_XPL_BUILD
|
||||
obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
|
||||
else
|
||||
obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o
|
||||
endif
|
||||
obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
|
||||
obj-$(CONFIG_$(XPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_XPL_BUILD
|
||||
obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1016,7 +1016,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
|
|||
* running however really wants to have dcache and the MMU active. Check that
|
||||
* everything is sane and give the developer a hint if it isn't.
|
||||
*/
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
#error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
obj-y += cpu.o
|
||||
obj-y += lowlevel.o
|
||||
obj-y += soc.o
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
ifndef CONFIG_XPL_BUILD
|
||||
obj-$(CONFIG_MP) += mp.o spintable.o
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ static struct mm_region early_map[] = {
|
|||
{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
|
||||
CFG_SYS_FSL_DRAM_SIZE1,
|
||||
#if defined(CONFIG_TFABOOT) || \
|
||||
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
|
||||
(defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD))
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
|
||||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
|
||||
|
|
@ -181,7 +181,7 @@ static struct mm_region early_map[] = {
|
|||
{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
|
||||
CFG_SYS_FSL_DRAM_SIZE1,
|
||||
#if defined(CONFIG_TFABOOT) || \
|
||||
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
|
||||
(defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD))
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
|
||||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
|
||||
|
|
@ -1055,7 +1055,7 @@ int cpu_eth_init(struct bd_info *bis)
|
|||
{
|
||||
int error = 0;
|
||||
|
||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
|
||||
error = fsl_mc_ldpaa_init(bis);
|
||||
#endif
|
||||
return error;
|
||||
|
|
@ -1285,7 +1285,7 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size)
|
|||
{
|
||||
phys_size_t ram_top = ram_size;
|
||||
|
||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
|
||||
ram_top = mc_get_dram_block_size();
|
||||
if (ram_top > ram_size)
|
||||
return ram_size + ram_top;
|
||||
|
|
@ -1381,7 +1381,7 @@ static int tfa_dram_init_banksize(void)
|
|||
if (i > 0)
|
||||
ret = 0;
|
||||
|
||||
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
|
||||
/* Assign memory for MC */
|
||||
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
|
||||
if (gd->bd->bi_dram[2].size >=
|
||||
|
|
@ -1467,7 +1467,7 @@ int dram_init_banksize(void)
|
|||
}
|
||||
#endif /* CFG_SYS_MEM_RESERVE_SECURE */
|
||||
|
||||
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
|
||||
/* Assign memory for MC */
|
||||
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
|
||||
if (gd->bd->bi_dram[2].size >=
|
||||
|
|
@ -1624,7 +1624,7 @@ __weak int dram_init(void)
|
|||
#ifdef CONFIG_SYS_FSL_DDR
|
||||
fsl_initdram();
|
||||
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
|
||||
defined(CONFIG_SPL_BUILD)
|
||||
defined(CONFIG_XPL_BUILD)
|
||||
/* This will break-before-make MMU for DDR */
|
||||
update_early_mmu_table();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
|
||||
#define HWA_CGA_M1_CLK_SEL 0xe0000000
|
||||
#define HWA_CGA_M1_CLK_SHIFT 29
|
||||
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD)
|
||||
rcw_tmp = in_be32(&gur->rcwsr[7]);
|
||||
switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
|
||||
case 2:
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
|
|||
static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
|
||||
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||
int xfi_dpmac[XFI14 + 1];
|
||||
int sgmii_dpmac[SGMII18 + 1];
|
||||
|
|
@ -162,7 +162,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
|
|||
debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
|
||||
else {
|
||||
serdes_prtcl_map[lane_prtcl] = 1;
|
||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
|
||||
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
|
||||
wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
|
||||
|
|
@ -553,7 +553,7 @@ int setup_serdes_volt(u32 svdd)
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
|
||||
int i , j;
|
||||
|
||||
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ static void set_icid(struct icid_id_table *tbl, int size)
|
|||
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD)
|
||||
static void set_fman_icids(struct fman_icid_id_table *tbl, int size)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -41,12 +41,12 @@ void set_icids(void)
|
|||
/* setup general icid offsets */
|
||||
set_icid(icid_tbl, icid_tbl_sz);
|
||||
|
||||
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD)
|
||||
set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
|
||||
{
|
||||
int i, ret;
|
||||
|
|
|
|||
|
|
@ -183,7 +183,7 @@ ENTRY(lowlevel_init)
|
|||
#endif
|
||||
|
||||
/* Initialize GIC Secure Bank Status */
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
#if !defined(CONFIG_XPL_BUILD)
|
||||
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
|
||||
branch_if_slave x0, 1f
|
||||
bl get_gic_offset
|
||||
|
|
@ -306,7 +306,7 @@ ENTRY(lowlevel_init)
|
|||
#endif
|
||||
|
||||
#if !defined(CONFIG_TFABOOT) && \
|
||||
(defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
|
||||
(defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_XPL_BUILD))
|
||||
bl fsl_ocram_init
|
||||
#endif
|
||||
|
||||
|
|
@ -314,7 +314,7 @@ ENTRY(lowlevel_init)
|
|||
ret
|
||||
ENDPROC(lowlevel_init)
|
||||
|
||||
#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_XPL_BUILD)
|
||||
ENTRY(fsl_ocram_init)
|
||||
mov x28, lr /* Save LR */
|
||||
bl fsl_clear_ocram
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ struct icid_id_table icid_tbl[] = {
|
|||
|
||||
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
|
||||
|
||||
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD)
|
||||
struct fman_icid_id_table fman_icid_tbl[] = {
|
||||
/* port id, icid */
|
||||
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = {
|
|||
|
||||
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
|
||||
|
||||
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD)
|
||||
struct fman_icid_id_table fman_icid_tbl[] = {
|
||||
/* port id, icid */
|
||||
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ u32 spl_boot_device(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
|
|
@ -136,4 +136,4 @@ int spl_start_uboot(void)
|
|||
return 1;
|
||||
}
|
||||
#endif /* CONFIG_SPL_OS_BOOT */
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
#endif /* CONFIG_XPL_BUILD */
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ reset:
|
|||
.globl save_boot_params_ret
|
||||
save_boot_params_ret:
|
||||
|
||||
#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_SPL_BUILD)
|
||||
#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_XPL_BUILD)
|
||||
/* Verify that we're 4K aligned. */
|
||||
adr x0, _start
|
||||
ands x0, x0, #0xfff
|
||||
|
|
@ -104,7 +104,7 @@ pie_skip_reloc:
|
|||
pie_fixup_done:
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_XPL_BUILD)
|
||||
.macro set_vbar, regname, reg
|
||||
msr \regname, \reg
|
||||
.endm
|
||||
|
|
@ -174,7 +174,7 @@ pie_fixup_done:
|
|||
/* Processor specific initialization */
|
||||
bl lowlevel_init
|
||||
|
||||
#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_XPL_BUILD)
|
||||
branch_if_master x0, master_cpu
|
||||
b spin_table_secondary_jump
|
||||
/* never return */
|
||||
|
|
@ -354,7 +354,7 @@ ENDPROC(smp_kick_all_cpus)
|
|||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
ENTRY(c_runtime_cpu_setup)
|
||||
#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_XPL_BUILD)
|
||||
/* Relocate vBAR */
|
||||
adr x0, vectors
|
||||
switch_el x1, 3f, 2f, 1f
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
};
|
||||
|
||||
&binman {
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
u-boot-spl-ddr {
|
||||
align = <4>;
|
||||
align-size = <4>;
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
};
|
||||
|
||||
&binman {
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
u-boot-spl-ddr {
|
||||
align = <4>;
|
||||
align-size = <4>;
|
||||
|
|
|
|||
|
|
@ -12,13 +12,13 @@
|
|||
#include <asm/armv8/sec_firmware.h>
|
||||
|
||||
struct icid_id_table {
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
const char *compat;
|
||||
phys_addr_t compat_addr;
|
||||
#endif
|
||||
phys_addr_t reg_addr;
|
||||
u32 reg;
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
u32 id;
|
||||
#endif
|
||||
bool le;
|
||||
|
|
@ -35,7 +35,7 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
|
|||
void set_icids(void);
|
||||
void fdt_fixup_icid(void *blob);
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
|
||||
{ .reg = regA, \
|
||||
.reg_addr = addr, \
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_XPL_BUILD)
|
||||
/*
|
||||
* We use absolute address not PC relative address to jump.
|
||||
* When running SPL on iMX8, the A core starts at address 0, a alias to OCRAM 0x100000,
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ void lpc32xx_slc_nand_init(void);
|
|||
void lpc32xx_i2c_init(unsigned int devnum);
|
||||
void lpc32xx_ssp_init(void);
|
||||
void lpc32xx_usb_init(void);
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_XPL_BUILD)
|
||||
void ddr_init(const struct emc_dram_settings *dram);
|
||||
#endif
|
||||
#endif /* _LPC32XX_SYS_PROTO_H */
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
|
||||
int litesom_mmc_init(struct bd_info *bis);
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
void litesom_init_f(void);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
#ifndef __ASM_ARCH_MX6_DDR_H__
|
||||
#define __ASM_ARCH_MX6_DDR_H__
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
#ifdef CONFIG_MX6Q
|
||||
#include "mx6q-ddr.h"
|
||||
#else
|
||||
|
|
@ -488,7 +488,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
|
|||
const struct mx6_mmdc_calibration *,
|
||||
const void *);
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
#endif /* CONFIG_XPL_BUILD */
|
||||
|
||||
#define MX6_MMDC_P0_MDCTL 0x021b0000
|
||||
#define MX6_MMDC_P0_MDPDC 0x021b0004
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int),
|
||||
int (*cd)(int));
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
|
||||
#if defined(CONFIG_MX23)
|
||||
#include <asm/arch/iomux-mx23.h>
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
* (containing the magic 'RK30'). This magic constant will be written into
|
||||
* the final image by the rkimage tool, but we need to reserve space for it here.
|
||||
*/
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
b 1f /* if overwritten, entry-address is at the next word */
|
||||
1:
|
||||
#endif
|
||||
|
|
@ -68,7 +68,7 @@ back_to_bootrom:
|
|||
pop {r1-r12, pc}
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SPL_BUILD))
|
||||
#if (defined(CONFIG_XPL_BUILD))
|
||||
/* U-Boot proper of armv7 does not need this */
|
||||
b reset
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
* To make life easier for everyone, we build the SPL binary with
|
||||
* space for this 4-byte header already included in the binary.
|
||||
*/
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
/*
|
||||
* We need to add 4 bytes of space for the 'RK33' at the
|
||||
* beginning of the executable. However, as we want to keep
|
||||
|
|
@ -39,7 +39,7 @@ entry_counter:
|
|||
.word 0
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64))
|
||||
#if (defined(CONFIG_XPL_BUILD) || defined(CONFIG_ARM64))
|
||||
/* U-Boot proper of armv7 do not need this */
|
||||
b reset
|
||||
#endif
|
||||
|
|
@ -54,7 +54,7 @@ _start:
|
|||
ARM_VECTORS
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \
|
||||
#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_XPL_BUILD) && \
|
||||
(CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
|
||||
.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#define KHz 1000
|
||||
#define OSC_HZ (24 * MHz)
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
|
||||
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
|
||||
#define APLL_HZ (1008 * MHz)
|
||||
#else
|
||||
#define APLL_HZ (816 * MHz)
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
#define CPLL_HZ (500 * MHz)
|
||||
#define HPLL_HZ (1400 * MHz)
|
||||
#define PCLK_PDPMU_HZ (100 * MHz)
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
|
||||
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
|
||||
#define ACLK_PDBUS_HZ (396 * MHz)
|
||||
#else
|
||||
#define ACLK_PDBUS_HZ (500 * MHz)
|
||||
|
|
@ -32,7 +32,7 @@
|
|||
#define HCLK_PDCORE_HZ (200 * MHz)
|
||||
#define HCLK_PDAUDIO_HZ (150 * MHz)
|
||||
#define CLK_OSC0_DIV_HZ (32768)
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
|
||||
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
|
||||
#define ACLK_PDVI_HZ (297 * MHz)
|
||||
#define CLK_ISP_HZ (297 * MHz)
|
||||
#define ACLK_PDISPP_HZ (297 * MHz)
|
||||
|
|
@ -324,7 +324,7 @@ enum {
|
|||
DCLK_VOP_DIV_SHIFT = 0,
|
||||
DCLK_VOP_DIV_MASK = 0xff,
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
|
||||
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
|
||||
/* CRU_CLK_SEL49_CON */
|
||||
ACLK_PDVI_SEL_SHIFT = 6,
|
||||
ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT,
|
||||
|
|
@ -397,7 +397,7 @@ enum {
|
|||
CLK_GMAC_SRC_DIV_SHIFT = 0,
|
||||
CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT,
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
|
||||
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
|
||||
/* CRU_CLK_SEL68_CON */
|
||||
ACLK_PDISPP_SEL_SHIFT = 6,
|
||||
ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT,
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_XPL_BUILD)
|
||||
/* reserve space for BOOT0 header information */
|
||||
b reset
|
||||
.space 1532
|
||||
|
|
@ -49,7 +49,7 @@
|
|||
.word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr
|
||||
.word SUNXI_SRAMC_BASE
|
||||
.word CONFIG_SUNXI_RVBAR_ALTERNATIVE // address for die variant
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
.word CONFIG_SPL_TEXT_BASE
|
||||
#else
|
||||
.word CONFIG_TEXT_BASE
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ void sdelay(unsigned long);
|
|||
void return_to_fel(uint32_t lr, uint32_t sp);
|
||||
|
||||
/* Board / SoC level designware gmac init */
|
||||
#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC
|
||||
#if !defined CONFIG_XPL_BUILD && defined CONFIG_SUN7I_GMAC
|
||||
void eth_init_board(void);
|
||||
#else
|
||||
static inline void eth_init_board(void) {}
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@
|
|||
#define __FSL_SECURE_BOOT_H
|
||||
|
||||
#ifdef CONFIG_CHAIN_OF_TRUST
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
|
||||
#endif /* #ifndef CONFIG_SPL_BUILD */
|
||||
#endif /* #ifndef CONFIG_XPL_BUILD */
|
||||
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ static inline u8 uboot_loaded_by_spl(void)
|
|||
*/
|
||||
static inline u32 omap_hw_init_context(void)
|
||||
{
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
return OMAP_INIT_CONTEXT_SPL;
|
||||
#else
|
||||
if (uboot_loaded_by_spl())
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ else
|
|||
obj-y += setjmp.o
|
||||
endif
|
||||
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
ifndef CONFIG_XPL_BUILD
|
||||
ifdef CONFIG_ARM64
|
||||
obj-y += relocate_64.o
|
||||
else
|
||||
|
|
@ -34,7 +34,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
|
|||
obj-$(CONFIG_CMD_BOOTM) += bootm.o
|
||||
obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o
|
||||
else
|
||||
obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o
|
||||
obj-$(CONFIG_$(PHASE_)FRAMEWORK) += spl.o
|
||||
ifdef CONFIG_SPL_FRAMEWORK
|
||||
obj-$(CONFIG_CMD_BOOTI) += image.o
|
||||
obj-$(CONFIG_CMD_BOOTZ) += zimage.o
|
||||
|
|
@ -42,14 +42,14 @@ endif
|
|||
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
|
||||
endif
|
||||
ifdef CONFIG_ARM64
|
||||
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o
|
||||
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o
|
||||
obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset-arm64.o
|
||||
obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy-arm64.o
|
||||
else
|
||||
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
|
||||
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
|
||||
obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset.o
|
||||
obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy.o
|
||||
endif
|
||||
obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o
|
||||
obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
|
||||
obj-$(CONFIG_$(PHASE_)SYS_L2_PL310) += cache-pl310.o
|
||||
obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += semihosting.o
|
||||
|
||||
ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),)
|
||||
obj-y += save_prev_bl_data.o
|
||||
|
|
@ -73,7 +73,7 @@ obj-y += interrupts_64.o
|
|||
else
|
||||
obj-y += interrupts.o
|
||||
endif
|
||||
ifndef CONFIG_$(SPL_TPL_)SYSRESET
|
||||
ifndef CONFIG_$(PHASE_)SYSRESET
|
||||
obj-y += reset.o
|
||||
endif
|
||||
|
||||
|
|
@ -94,7 +94,7 @@ endif
|
|||
|
||||
# some files can only build in ARM or THUMB2, not THUMB1
|
||||
|
||||
ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
|
||||
ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
|
||||
asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL
|
||||
ifndef CONFIG_HAS_THUMB2
|
||||
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ int check_cache_range(unsigned long start, unsigned long stop)
|
|||
ok = 0;
|
||||
|
||||
if (!ok) {
|
||||
warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
|
||||
warn_non_xpl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
|
||||
start, stop);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ ENTRY(_main)
|
|||
|
||||
#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
|
||||
ldr r0, =(CONFIG_TPL_STACK)
|
||||
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
|
||||
#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
|
||||
ldr r0, =(CONFIG_SPL_STACK)
|
||||
#else
|
||||
ldr r0, =(SYS_INIT_SP_ADDR)
|
||||
|
|
@ -119,14 +119,14 @@ ENTRY(_main)
|
|||
bl debug_uart_init
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS)
|
||||
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS)
|
||||
CLEAR_BSS
|
||||
#endif
|
||||
|
||||
mov r0, #0
|
||||
bl board_init_f
|
||||
|
||||
#if ! defined(CONFIG_SPL_BUILD)
|
||||
#if ! defined(CONFIG_XPL_BUILD)
|
||||
|
||||
/*
|
||||
* Set up intermediate environment (new sp and gd) and call
|
||||
|
|
@ -171,13 +171,13 @@ here:
|
|||
|
||||
bl c_runtime_cpu_setup /* we still call old routine here */
|
||||
#endif
|
||||
#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK)
|
||||
#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK)
|
||||
|
||||
#if !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS)
|
||||
#if !defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS)
|
||||
CLEAR_BSS
|
||||
#endif
|
||||
|
||||
# ifdef CONFIG_SPL_BUILD
|
||||
# ifdef CONFIG_XPL_BUILD
|
||||
/* Use a DRAM stack for the rest of SPL, if requested */
|
||||
bl spl_relocate_stack_gd
|
||||
cmp r0, #0
|
||||
|
|
@ -185,7 +185,7 @@ here:
|
|||
movne r9, r0
|
||||
# endif
|
||||
|
||||
#if ! defined(CONFIG_SPL_BUILD)
|
||||
#if ! defined(CONFIG_XPL_BUILD)
|
||||
bl coloured_LED_init
|
||||
bl red_led_on
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ ENTRY(_main)
|
|||
*/
|
||||
#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
|
||||
ldr x0, =(CONFIG_TPL_STACK)
|
||||
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
|
||||
#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
|
||||
ldr x0, =(CONFIG_SPL_STACK)
|
||||
#elif defined(CONFIG_INIT_SP_RELATIVE)
|
||||
#if CONFIG_POSITION_INDEPENDENT
|
||||
|
|
@ -99,7 +99,7 @@ ENTRY(_main)
|
|||
mov x0, #0
|
||||
bl board_init_f
|
||||
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
#if !defined(CONFIG_XPL_BUILD)
|
||||
/*
|
||||
* Set up intermediate environment (new sp and gd) and call
|
||||
* relocate_code(addr_moni). Trick here is that we'll return
|
||||
|
|
@ -139,9 +139,9 @@ relocation_return:
|
|||
* Set up final (full) environment
|
||||
*/
|
||||
bl c_runtime_cpu_setup /* still call old routine */
|
||||
#endif /* !CONFIG_SPL_BUILD */
|
||||
#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK)
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
#endif /* !CONFIG_XPL_BUILD */
|
||||
#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK)
|
||||
#if defined(CONFIG_XPL_BUILD)
|
||||
bl spl_relocate_stack_gd /* may return NULL */
|
||||
/* set up gd here, outside any C code, if new stack is returned */
|
||||
cmp x0, #0
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
int raise (int signum)
|
||||
{
|
||||
/* Even if printf() is available, it's large. Punt it for SPL builds */
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
#if !defined(CONFIG_XPL_BUILD)
|
||||
printf("raise: Signal # %d caught\n", signum);
|
||||
#endif
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
int arch_reserve_stacks(void)
|
||||
{
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */
|
||||
gd->irq_sp = gd->start_addr_sp;
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ _fiq: .word fiq
|
|||
|
||||
/* SPL interrupt handling: just hang */
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
|
||||
#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE)
|
||||
.align 5
|
||||
|
|
@ -166,7 +166,7 @@ fiq:
|
|||
b 1b /* hang and never return */
|
||||
#endif
|
||||
|
||||
#else /* !CONFIG_SPL_BUILD */
|
||||
#else /* !CONFIG_XPL_BUILD */
|
||||
|
||||
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||
.globl IRQ_STACK_START_IN
|
||||
|
|
@ -332,4 +332,4 @@ fiq:
|
|||
bad_save_user_regs
|
||||
bl do_fiq
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
#endif /* CONFIG_XPL_BUILD */
|
||||
|
|
|
|||
|
|
@ -24,14 +24,14 @@ int bootz_setup(ulong image, ulong *start, ulong *end)
|
|||
|
||||
if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC &&
|
||||
zi->zi_magic != BAREBOX_IMAGE_MAGIC) {
|
||||
if (!IS_ENABLED(CONFIG_SPL_BUILD))
|
||||
if (!IS_ENABLED(CONFIG_XPL_BUILD))
|
||||
puts("zimage: Bad magic!\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
*start = zi->zi_start;
|
||||
*end = zi->zi_end;
|
||||
if (!IS_ENABLED(CONFIG_SPL_BUILD))
|
||||
if (!IS_ENABLED(CONFIG_XPL_BUILD))
|
||||
printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n",
|
||||
image, *start, *end);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
obj-y += lowlevel_init.o board_common.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||
obj-$(CONFIG_XPL_BUILD) += spl.o
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@
|
|||
.globl lowlevel_init
|
||||
|
||||
lowlevel_init:
|
||||
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
|
||||
mov pc, lr
|
||||
#else
|
||||
/* setup ARM arch timer frequency */
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
|
||||
ifneq ($(CONFIG_SPL_BUILD),)
|
||||
ifneq ($(CONFIG_XPL_BUILD),)
|
||||
obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o
|
||||
obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
|
||||
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
|
|||
obj-$(CONFIG_SAM9X60) += sam9x60_devices.o
|
||||
obj-y += clock.o
|
||||
obj-y += cpu.o
|
||||
ifndef CONFIG_$(SPL_TPL_)SYSRESET
|
||||
ifndef CONFIG_$(PHASE_)SYSRESET
|
||||
obj-y += reset.o
|
||||
endif
|
||||
ifneq ($(CONFIG_ATMEL_PIT_TIMER),y)
|
||||
|
|
@ -32,7 +32,7 @@ obj-y += lowlevel_init.o
|
|||
endif
|
||||
endif
|
||||
|
||||
ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
|
||||
ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
|
||||
ifndef CONFIG_HAS_THUMB2
|
||||
|
||||
CFLAGS_cache.o := -marm
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
|
|||
endif
|
||||
|
||||
ifeq ($(CONFIG_CPU_V7A),y)
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
ifndef CONFIG_XPL_BUILD
|
||||
INPUTS-y += u-boot.img
|
||||
endif
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ obj-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o
|
|||
obj-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
|
||||
obj-$(CONFIG_SOC_DA850) += da850_pinmux.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_XPL_BUILD
|
||||
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
|
||||
obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2012, Texas Instruments, Incorporated - https://www.ti.com/
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
ifndef CONFIG_XPL_BUILD
|
||||
INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ obj-$(CONFIG_ARM64) += mmu-arm64.o
|
|||
|
||||
obj-$(CONFIG_EXYNOS5420) += sec_boot.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_XPL_BUILD
|
||||
obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
|
||||
obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
|
||||
|
|
|
|||
|
|
@ -221,8 +221,8 @@ int do_lowlevel_init(void)
|
|||
if (actions & DO_CLOCKS) {
|
||||
system_clock_init();
|
||||
#ifdef CONFIG_DEBUG_UART
|
||||
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \
|
||||
!defined(CONFIG_SPL_BUILD)
|
||||
#if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \
|
||||
!defined(CONFIG_XPL_BUILD)
|
||||
exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
|
||||
debug_uart_init();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ static int exynos5420_mmc_config(int peripheral, int flags)
|
|||
* this same assumption.
|
||||
*/
|
||||
if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
gpio_request(i, "sdmmc0_vdden");
|
||||
#endif
|
||||
gpio_set_value(i, 1);
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ obj-y = iomux-v3.o
|
|||
endif
|
||||
|
||||
ifeq ($(SOC),$(filter $(SOC),imx8m))
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ifneq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
|
||||
endif
|
||||
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
|
||||
|
|
@ -22,7 +22,7 @@ obj-y += cpu.o
|
|||
endif
|
||||
|
||||
ifeq ($(SOC),$(filter $(SOC),imx8m imx9))
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ifneq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-y += fdt.o
|
||||
endif
|
||||
endif
|
||||
|
|
@ -38,7 +38,7 @@ endif
|
|||
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imx9 imxrt))
|
||||
obj-y += misc.o
|
||||
obj-$(CONFIG_CMD_PRIBLOB) += priblob.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||
obj-$(CONFIG_XPL_BUILD) += spl.o
|
||||
endif
|
||||
ifeq ($(SOC),$(filter $(SOC),mx7))
|
||||
obj-y += cpu.o
|
||||
|
|
@ -46,7 +46,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
|
|||
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
|
||||
endif
|
||||
ifeq ($(SOC),$(filter $(SOC),mx7 imx8m))
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ifneq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o
|
||||
endif
|
||||
endif
|
||||
|
|
@ -57,10 +57,10 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
|
|||
obj-y += cache.o init.o
|
||||
obj-$(CONFIG_FEC_MXC) += mac.o
|
||||
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ifneq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
|
||||
endif
|
||||
obj-$(CONFIG_$(SPL_)SATA) += sata.o
|
||||
obj-$(CONFIG_$(XPL_)SATA) += sata.o
|
||||
obj-$(CONFIG_IMX_HAB) += hab.o
|
||||
obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
|
||||
endif
|
||||
|
|
@ -73,18 +73,18 @@ obj-y += ddrmc-vf610.o
|
|||
obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o
|
||||
endif
|
||||
ifeq ($(SOC),$(filter $(SOC),imx8))
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ifneq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
|
||||
endif
|
||||
endif
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ifneq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
|
||||
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
|
||||
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
|
||||
obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SPL_BUILD),y)
|
||||
ifeq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o
|
||||
endif
|
||||
|
||||
|
|
@ -128,7 +128,7 @@ container.cfg: $(IMX_CONTAINER_CFG) FORCE
|
|||
ifeq ($(CONFIG_ARCH_IMX8), y)
|
||||
CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
|
||||
IMAGE_TYPE := imx8image
|
||||
ifeq ($(CONFIG_SPL_BUILD),y)
|
||||
ifeq ($(CONFIG_XPL_BUILD),y)
|
||||
SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi)
|
||||
endif
|
||||
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ u32 get_imx_reset_cause(void)
|
|||
if (reset_cause == -1) {
|
||||
reset_cause = readl(&src_regs->srsr);
|
||||
/* preserve the value for U-Boot proper */
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
#if !defined(CONFIG_XPL_BUILD)
|
||||
writel(reset_cause, &src_regs->srsr);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -47,7 +47,7 @@ u32 get_imx_reset_cause(void)
|
|||
return reset_cause;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD)
|
||||
static char *get_reset_cause(void)
|
||||
{
|
||||
switch (get_imx_reset_cause()) {
|
||||
|
|
@ -92,7 +92,7 @@ static char *get_reset_cause(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD)
|
||||
|
||||
const char *get_imx_type(u32 imxtype)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -245,7 +245,7 @@ void *hab_rvt_authenticate_image(uint8_t cid, ptrdiff_t ivt_offset,
|
|||
return ret;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
#if !defined(CONFIG_XPL_BUILD)
|
||||
|
||||
#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
|
||||
|
||||
|
|
@ -727,7 +727,7 @@ U_BOOT_CMD(
|
|||
""
|
||||
);
|
||||
|
||||
#endif /* !defined(CONFIG_SPL_BUILD) */
|
||||
#endif /* !defined(CONFIG_XPL_BUILD) */
|
||||
|
||||
/* Get CSF Header length */
|
||||
static int get_hab_hdr_len(struct hab_hdr *hdr)
|
||||
|
|
@ -939,7 +939,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
|
|||
puts("Dumping CSF Header\n");
|
||||
print_buffer(ivt->csf, (void *)(uintptr_t)(ivt->csf), 4, 0x10, 0);
|
||||
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
#if !defined(CONFIG_XPL_BUILD)
|
||||
get_hab_status();
|
||||
#endif
|
||||
|
||||
|
|
@ -989,7 +989,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
|
|||
}
|
||||
|
||||
hab_exit_failure_print_status:
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
#if !defined(CONFIG_XPL_BUILD)
|
||||
get_hab_status();
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -89,11 +89,11 @@ __weak void reset_cpu(void)
|
|||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
|
||||
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
|
||||
spl_save_restore_data();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
struct pass_over_info_t *pass_over;
|
||||
|
||||
if (is_soc_rev(CHIP_REV_A)) {
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
|
||||
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
|
||||
PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
|
||||
|
|
|
|||
|
|
@ -611,7 +611,7 @@ void dram_disable_bypass(void)
|
|||
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
void dram_pll_init(ulong pll_val)
|
||||
{
|
||||
u32 val;
|
||||
|
|
@ -791,7 +791,7 @@ int clock_init(void)
|
|||
/*
|
||||
* Dump some clockes.
|
||||
*/
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[])
|
||||
{
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
|
|||
|
||||
int timer_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
|
||||
unsigned long freq = readl(&sctr->cntfid0);
|
||||
|
||||
|
|
@ -255,7 +255,7 @@ int dram_init(void)
|
|||
return ret;
|
||||
|
||||
/* rom_pointer[1] contains the size of TEE occupies */
|
||||
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1])
|
||||
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1])
|
||||
gd->ram_size = sdram_size - rom_pointer[1];
|
||||
else
|
||||
gd->ram_size = sdram_size;
|
||||
|
|
@ -284,7 +284,7 @@ int dram_init_banksize(void)
|
|||
}
|
||||
|
||||
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
|
||||
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
|
||||
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
|
||||
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
|
||||
phys_size_t optee_size = (size_t)rom_pointer[1];
|
||||
|
||||
|
|
@ -329,7 +329,7 @@ phys_size_t get_effective_memsize(void)
|
|||
sdram_b1_size = sdram_size;
|
||||
}
|
||||
|
||||
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) &&
|
||||
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) &&
|
||||
rom_pointer[1]) {
|
||||
/* We will relocate u-boot to Top of dram1. Tee position has two cases:
|
||||
* 1. At the top of dram1, Then return the size removed optee size.
|
||||
|
|
@ -612,7 +612,7 @@ static void early_enable_caches(void)
|
|||
phys_size_t sdram_size;
|
||||
int entry, ret;
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD))
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD))
|
||||
return;
|
||||
|
||||
if (CONFIG_IS_ENABLED(SYS_ICACHE_OFF) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
|
||||
|
|
@ -646,7 +646,7 @@ int arch_cpu_init(void)
|
|||
* ROM might disable clock for SCTR,
|
||||
* enable the clock before timer_init.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD))
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD))
|
||||
clock_enable(CCGR_SCTR, 1);
|
||||
/*
|
||||
* Init timer at very early state, because sscg pll setting
|
||||
|
|
@ -654,7 +654,7 @@ int arch_cpu_init(void)
|
|||
*/
|
||||
timer_init();
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD)) {
|
||||
clock_init();
|
||||
imx_set_wdog_powerdown(false);
|
||||
|
||||
|
|
@ -1477,7 +1477,7 @@ int arch_misc_init(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_XPL_BUILD)
|
||||
#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
|
||||
bool serror_need_skip = true;
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,6 @@
|
|||
obj-y += lowlevel_init.o
|
||||
obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o
|
||||
|
||||
ifeq ($(CONFIG_SPL_BUILD),y)
|
||||
ifeq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-y += upower/
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -519,7 +519,7 @@ u32 get_lpuart_clk(void)
|
|||
return pcc_clock_get_rate(lpuart_pcc[index], lpuart_pcc_slots[index]);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
/*
|
||||
* Dump some core clockes.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ rom_pointer:
|
|||
|
||||
.global save_boot_params
|
||||
save_boot_params:
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
/* The firmware provided ATAG/FDT address can be found in r2/x0 */
|
||||
adr x0, rom_pointer
|
||||
stp x1, x2, [x0], #16
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@ enum bt_mode get_boot_mode(void)
|
|||
|
||||
bool m33_image_booted(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD)) {
|
||||
u32 gp6 = 0;
|
||||
|
||||
/* DGO_GP6 */
|
||||
|
|
@ -124,7 +124,7 @@ bool m33_image_booted(void)
|
|||
|
||||
bool rdc_enabled_in_boot(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD)) {
|
||||
u32 val = 0;
|
||||
int ret;
|
||||
bool rdc_en = true; /* Default assume DBD_EN is set */
|
||||
|
|
@ -146,7 +146,7 @@ bool rdc_enabled_in_boot(void)
|
|||
|
||||
static void spl_pass_boot_info(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD)) {
|
||||
bool m33_booted = m33_image_booted();
|
||||
bool rdc_en = rdc_enabled_in_boot();
|
||||
u32 val = 0;
|
||||
|
|
@ -164,7 +164,7 @@ static void spl_pass_boot_info(void)
|
|||
bool is_m33_handshake_necessary(void)
|
||||
{
|
||||
/* Only need handshake in u-boot */
|
||||
if (!IS_ENABLED(CONFIG_SPL_BUILD))
|
||||
if (!IS_ENABLED(CONFIG_XPL_BUILD))
|
||||
return (m33_image_booted() || rdc_enabled_in_boot());
|
||||
else
|
||||
return false;
|
||||
|
|
@ -716,7 +716,7 @@ void set_lpav_qos(void)
|
|||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD)) {
|
||||
/* Enable System Reset Interrupt using WDOG_AD */
|
||||
setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
|
||||
/* Clear AD_PERIPH Power switch domain out of reset interrupt flag */
|
||||
|
|
@ -805,7 +805,7 @@ int imx8ulp_dm_post_init(void)
|
|||
}
|
||||
EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init);
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_XPL_BUILD)
|
||||
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
|
||||
{
|
||||
debug("image entry point: 0x%lx\n", spl_image->entry_point);
|
||||
|
|
|
|||
|
|
@ -5,6 +5,6 @@
|
|||
obj-y += lowlevel_init.o
|
||||
obj-y += soc.o clock.o clock_root.o trdc.o
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
obj-y += imx_bootaux.o
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -640,7 +640,7 @@ void enable_usboh3_clk(unsigned char enable)
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
void dram_pll_init(ulong pll_val)
|
||||
{
|
||||
configure_fracpll(DRAM_PLL_CLK, pll_val);
|
||||
|
|
@ -950,7 +950,7 @@ int set_clk_enet(enum enet_freq type)
|
|||
/*
|
||||
* Dump some clockes.
|
||||
*/
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
u32 freq;
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ rom_pointer:
|
|||
|
||||
.global save_boot_params
|
||||
save_boot_params:
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
/* The firmware provided ATAG/FDT address can be found in r2/x0 */
|
||||
adr x0, rom_pointer
|
||||
stp x1, x2, [x0], #16
|
||||
|
|
|
|||
|
|
@ -383,7 +383,7 @@ int dram_init(void)
|
|||
return ret;
|
||||
|
||||
/* rom_pointer[1] contains the size of TEE occupies */
|
||||
if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1])
|
||||
if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1])
|
||||
gd->ram_size = sdram_size - rom_pointer[1];
|
||||
else
|
||||
gd->ram_size = sdram_size;
|
||||
|
|
@ -412,7 +412,7 @@ int dram_init_banksize(void)
|
|||
}
|
||||
|
||||
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
|
||||
if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
|
||||
if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
|
||||
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
|
||||
phys_size_t optee_size = (size_t)rom_pointer[1];
|
||||
|
||||
|
|
@ -457,7 +457,7 @@ phys_size_t get_effective_memsize(void)
|
|||
else
|
||||
sdram_b1_size = sdram_size;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
|
||||
if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
|
||||
/* We will relocate u-boot to top of dram1. TEE position has two cases:
|
||||
* 1. At the top of dram1, Then return the size removed optee size.
|
||||
* 2. In the middle of dram1, return the size of dram1.
|
||||
|
|
@ -629,7 +629,7 @@ static int low_drive_freq_update(void *blob)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_FIXUP
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
int board_fix_fdt(void *fdt)
|
||||
{
|
||||
/* Update dtb clocks for low drive mode */
|
||||
|
|
@ -701,7 +701,7 @@ static void save_reset_cause(void)
|
|||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD)) {
|
||||
/* Disable wdog */
|
||||
init_wdog();
|
||||
|
||||
|
|
@ -745,7 +745,7 @@ EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu);
|
|||
|
||||
int timer_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
|
||||
unsigned long freq = readl(&sctr->cntfid0);
|
||||
|
||||
|
|
|
|||
|
|
@ -940,7 +940,7 @@ void mxc_set_sata_internal_clock(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
/*
|
||||
* Dump some core clockes.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
|
||||
obj-y := soc.o clock.o
|
||||
obj-$(CONFIG_IMX_MODULE_FUSE) += module_fuse.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr.o
|
||||
obj-$(CONFIG_XPL_BUILD) += ddr.o
|
||||
obj-$(CONFIG_MP) += mp.o
|
||||
obj-$(CONFIG_MX6UL_LITESOM) += litesom.o
|
||||
obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o
|
||||
|
|
|
|||
|
|
@ -1367,7 +1367,7 @@ void disable_ipu_clock(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
/*
|
||||
* Dump some core clockes.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ int litesom_mmc_init(struct bd_info *bis)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
#include <linux/libfdt.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ int dram_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <spl.h>
|
||||
|
|
@ -210,4 +210,4 @@ void board_init_f(ulong dummy)
|
|||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
}
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
#endif /* CONFIG_XPL_BUILD */
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ struct scu_regs {
|
|||
u32 fpga_rev;
|
||||
};
|
||||
|
||||
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_THERMAL)
|
||||
#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX_THERMAL)
|
||||
static const struct imx_thermal_plat imx6_thermal_plat = {
|
||||
.regs = (void *)ANATOP_BASE_ADDR,
|
||||
.fuse_bank = 1,
|
||||
|
|
@ -565,7 +565,7 @@ int board_postclk_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
/*
|
||||
* cfg_val will be used for
|
||||
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
|
||||
|
|
@ -600,7 +600,7 @@ const struct boot_mode soc_boot_modes[] = {
|
|||
|
||||
void reset_misc(void)
|
||||
{
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
|
||||
lcdif_power_down();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1100,7 +1100,7 @@ void epdc_clock_disable(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
/*
|
||||
* Dump some core clockes.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -432,7 +432,7 @@ void s_init(void)
|
|||
return;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
const struct boot_mode soc_boot_modes[] = {
|
||||
{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
|
||||
{"primary", MAKE_CFGVAL_PRIMARY_BOOT},
|
||||
|
|
@ -450,7 +450,7 @@ int boot_mode_getprisec(void)
|
|||
|
||||
void reset_misc(void)
|
||||
{
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
|
||||
lcdif_power_down();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -327,7 +327,7 @@ void hab_caam_clock_enable(unsigned char enable)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_XPL_BUILD
|
||||
/*
|
||||
* Dump some core clockes.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ static bool ldo_mode_is_enabled(void)
|
|||
return false;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
|
||||
#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_XPL_BUILD))
|
||||
#if defined(CONFIG_LDO_ENABLED_MODE)
|
||||
static void init_ldo_mode(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec)
|
|||
return usec;
|
||||
}
|
||||
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_SPL_BUILD)
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_XPL_BUILD)
|
||||
int timer_init(void)
|
||||
{
|
||||
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
|
||||
|
|
|
|||
|
|
@ -4,4 +4,4 @@
|
|||
# Andrew Davis <afd@ti.com>
|
||||
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += am62a7_fdt.o
|
||||
obj-$(CONFIG_SPL_BUILD) += am62a7_init.o
|
||||
obj-$(CONFIG_XPL_BUILD) += am62a7_init.o
|
||||
|
|
|
|||
|
|
@ -4,4 +4,4 @@
|
|||
# Andrew Davis <afd@ti.com>
|
||||
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += am62p5_fdt.o
|
||||
obj-$(CONFIG_SPL_BUILD) += am62p5_init.o
|
||||
obj-$(CONFIG_XPL_BUILD) += am62p5_init.o
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += am625_fdt.o
|
||||
obj-$(CONFIG_SPL_BUILD) += am625_init.o
|
||||
obj-$(CONFIG_XPL_BUILD) += am625_init.o
|
||||
obj-y += boot.o
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += am642_init.o
|
||||
obj-$(CONFIG_XPL_BUILD) += am642_init.o
|
||||
obj-y += boot.o
|
||||
|
|
|
|||
|
|
@ -4,4 +4,4 @@
|
|||
# Andrew Davis <afd@ti.com>
|
||||
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += am654_fdt.o
|
||||
obj-$(CONFIG_SPL_BUILD) += am654_init.o
|
||||
obj-$(CONFIG_XPL_BUILD) += am654_init.o
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
#include <config.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_XPL_BUILD)
|
||||
ENTRY(__asm_invalidate_l3_dcache)
|
||||
/* Invalidate SPL address range */
|
||||
mov x0, #CONFIG_SPL_TEXT_BASE
|
||||
|
|
|
|||
|
|
@ -4,4 +4,4 @@
|
|||
# Andrew Davis <afd@ti.com>
|
||||
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += j721e_fdt.o
|
||||
obj-$(CONFIG_SPL_BUILD) += j721e_init.o
|
||||
obj-$(CONFIG_XPL_BUILD) += j721e_init.o
|
||||
|
|
|
|||
|
|
@ -4,4 +4,4 @@
|
|||
# Andrew Davis <afd@ti.com>
|
||||
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += j721s2_fdt.o
|
||||
obj-$(CONFIG_SPL_BUILD) += j721s2_init.o
|
||||
obj-$(CONFIG_XPL_BUILD) += j721s2_init.o
|
||||
|
|
|
|||
|
|
@ -312,7 +312,7 @@ void do_dt_magic(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
k3_spl_init();
|
||||
|
|
|
|||
|
|
@ -4,4 +4,4 @@
|
|||
# Jayesh Choudhary <j-choudhary@ti.com>
|
||||
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += j722s_fdt.o
|
||||
obj-$(CONFIG_SPL_BUILD) += j722s_init.o
|
||||
obj-$(CONFIG_XPL_BUILD) += j722s_init.o
|
||||
|
|
|
|||
|
|
@ -4,4 +4,4 @@
|
|||
# Andrew Davis <afd@ti.com>
|
||||
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += j784s4_fdt.o
|
||||
obj-$(CONFIG_SPL_BUILD) += j784s4_init.o
|
||||
obj-$(CONFIG_XPL_BUILD) += j784s4_init.o
|
||||
|
|
|
|||
|
|
@ -16,6 +16,6 @@ obj-y += common.o
|
|||
obj-y += lowlevel_init.o
|
||||
obj-y += r5_mpu.o
|
||||
|
||||
ifeq ($(CONFIG_SPL_BUILD),y)
|
||||
ifeq ($(CONFIG_XPL_BUILD),y)
|
||||
obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
|
||||
endif
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue