Maheedhar Bollapalli e5e417ddec fix(versal-net): handle invalid entry point in cpu hotplug scenario ... Invalid addresses are from 2G-4G and also address where TF-A is. Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4 Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>		2025-03-26 06:33:21 +00:00
..
aarch64	fix(versal-net): modify function to have single return	2025-01-22 04:07:35 +00:00
include	fix(versal-net): handle invalid entry point in cpu hotplug scenario	2025-03-26 06:33:21 +00:00
pm_service	Merge "fix(versal-net): remove_redundant_lock_defs" into integration	2025-01-30 16:32:41 +01:00
tsp	build(versal-net): reorganize platform source files	2023-12-04 05:52:07 +01:00
bl31_versal_net_setup.c	Merge changes from topic "xlnx_fix_plat_single_ret" into integration	2025-01-23 11:22:47 +01:00
plat_psci.c	fix(versal-net): use arm common GIC handlers	2024-01-09 00:38:21 -08:00
plat_psci_pm.c	fix(versal-net): handle invalid entry point in cpu hotplug scenario	2025-03-26 06:33:21 +00:00
plat_topology.c	fix(versal-net): modify function to have single return	2025-01-22 04:07:35 +00:00
platform.mk	refactor(xilinx): refactor console to support transfer list	2025-02-17 06:11:10 +00:00
sip_svc_setup.c	fix(versal-net): add unsigned suffix to match data type	2024-12-23 09:14:16 +00:00
versal_net_ipi.c	feat(versal-net): add bufferless IPI Support	2023-12-05 06:59:51 +01:00