Invalid addresses are from 2G-4G and also address where TF-A is.
Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
or makefile where XLNX_DT_CFG macro describe if system is DT driven or not.
Change-Id: Id45c03a950b62e83e91a50e0485eacdb233ba745
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(versal): modify function to have single return
fix(xilinx): modify function to have single return
fix(zynqmp): modify function to have single return
fix(versal-net): add unsigned suffix to match data type
fix(versal): add unsigned suffix to match data type
fix(versal2): add missing curly braces
fix(versal-net): add missing curly braces
fix(zynqmp): add missing curly braces
This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.
Change-Id: Ib8b3339f32031a3657f6c349763a20a99fd828e7
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
The commit a6485b2b3b ("refactor(delay-timer): add timer
callback functions") is breaking DCC console due to uninitialized
timer ops structure. Fix it by moving generic delay timer init
prior to console setup to make sure that time is setup before DCC
console setup.
Fixes: a6485b2b3b ("refactor(delay-timer): add timer callback
functions")
Change-Id: I67910332773741c0b08f02feb232efab6356db12
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type.
Appended "u" suffix to integer constant to represent it as
unsigned type.
Change-Id: I08b055134d6bd0380cca1e5b6ee527d6045a76c5
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.
Change-Id: I8de33e774178720411313021a7b157045d3cefa0
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: Ie2d32d5554d251cde8a9c8b7c7a85666ea505a15
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: If0a6ffa84c4d1ce5ae08337a4eb20c9a221d7795
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I5add78285ff0e48aa6c0fb639e7e2924f5bf9000
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
HW_ASSISTED_COHERENCY is always enabled on cortex a78
based versal-net platform.
hence remove the redundant definitions for pm_client_lock_get
and pm_client_lock_release.
Change-Id: Ifcf1bca0d494cfeb4ca23f6c884dfa5a347f786b
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
This corrects the MISRA violation C2012-5.8:
Identifiers that define objects or functions with
external linkage shall be unique.
Modify the variable name to prevent conflict with
external object linkage.
Change-Id: Icba1860d789d3826a58b3d83b65ca86a7b364c46
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This correct MISRA violation C2012-17.7:
The value returned by a function having non-void return type shall
be used.
Typecast the function call to void to discard the return value.
Change-Id: I670b476ba16e791e46aaa00feca991e1a4fff227
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-14.4:
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially
boolean type.
Updated controlling expression to explicitly compare with zero.
Change-Id: If5d9e8400e6c41cbe9e9c69d810fa62192f02bf3
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-12.1:
The precedence of operators within expressions should be
made explicit.
Enclosed the subexpression in parentheses to maintain
the precedence.
Change-Id: I3c30f5029628f8b297c08443a2c6c8bbf2063d29
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
None console does not register boot and runtime console.
User will not observe any console logs.
Change-Id: I39877c900f399ae7cffc1bb599b30c7a23888fc8
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
In the platform.mk file, new console types named dtb
are to be created a macro, VERSAL_NET_CONSOLE_ID_dtb, will
be introduced to check DT console.Users will have the
option to select VERSAL_NET_CONSOLE to dtb, which will run
from the DDR address and OCM. The address XILINX_OF_BOARD_DTB_ADDR
needs to be provided. This configuration will register the
DT console in TF-A
Change-Id: I530492c3f48705387e50895aef4bf229a82d350d
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
Introduce a build-time parameter (CONSOLE_RUNTIME) to select
separate runtime console options. For boot-time console, remove
the runtime flag and add a boot/crash flag. Additionally,
introduce an RT_CONSOLE_IS macro to check different UART types.
Implement a common function, console_runtime_init(), to initialize
the runtime console. Ensure that all platforms have access to
this feature.
The current implementation utilizes a single console for boot,
crash, and runtime. Make sure that the dedicated console integrates
into runtime and crash scenarios
Change-Id: I49b8554c0f067c85eb693e039a0cf17c5e6794ce
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
This corrects the MISRA violation C2012-11.9:
The macro NULL shall be the only permitted form of integer
null pointer constant.
The condition is compared with NULL to get boolean result.
Change-Id: Iff25e69c646337867caad0d992d814c3cd4260cf
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.
Change-Id: I20ef3be35f88649979d577ec8be4357813d4c1b7
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
Comment is not showing correct macro name that's why fix it.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I8bc38534309285af8a27ee43782e03e9d0470267
SMC ID is fixed in new SiP SVC call format while it varies according
to PLM header in old Linux. So, enhance SIP_SVC_VERSION number to
support backward compatibility and to use full request and response
buffer from bare-metal or Linux.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I6764cc92b33b7366640f553827e80c5e97985fcf
Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.
So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071
With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl32
load address is indicated as 0 in handoff is removed.
Change-Id: Ie927787129816e79d43ba4803f6916e20d81458a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
arm clusterbusqos register has a default value of 0xeeeeeeee.
this may create bottleneck for other masters in system when
accessing other memories including ddr.
hence clusterbusqos is setup to lowest value 0.
Change-Id: I73d55066eb84e198c8c69593bb5700745f04f290
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Refactor console_flush() and console_switch_state(CONSOLE_FLAG_RUNTIME)
to bl31_main(). This has been done per the recommendation in TF-A
mailing list. These calls need to be the last calls, after any runtime
initialization has been done, before BL31 exits.
All platforms that override the generic implementation of
bl31_plat_runtime_setup() have been refactored. The console_flush()
and console_switch_state() calls have been removed as they become
part of bl31_main() function.
Any platform that don't need to make any change to the generic (weak)
implementation of bl31_plat_runtime_setup() don't need to override it
in their platforms.
Change-Id: I6d04d6daa9353daeaa7e3df9e9adf6f322a917b8
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.
This patch affects Xilinx SoCs only.
Change-Id: Iea4cf920934bbde4312f40c8c7b3e0f56a316e86
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
As per the MISRA-C standards, there should be proc == NULL not just
!proc.
Fix the same.
Change-Id: I0e7650c09b045882a0235869d7ef9fca27f96d9a
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Check return value from pm_get_proc() to make sure that CPU is valid.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If51b5d42ce87f31fd732ab58ae8fcd0e2db0a2a8
* changes:
fix(xilinx): add console_flush() before shutdown
fix(xilinx): fix sending sgi to linux
feat(xilinx): add new state to identify cpu power down
feat(xilinx): request cpu power down from reset
feat(xilinx): power down all cores on receiving cpu pwrdwn req
feat(xilinx): add handler for power down req sgi irq
feat(xilinx): add wrapper to handle cpu power down req
fix(versal-net): use arm common GIC handlers
fix(xilinx): rename macros to align with ARM
As per SMCCC Section 6.2, the call count query for all the services
has been deprecated from SMCCC v1.2 onwards.
Inline with above change, AMD-Xilinx SiP service count query has
been deprecated and now onwards will return unknown function
identifier error.
Change-Id: I296d119d65549fdb01718d08351d255550e4ead0
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Currently there is only 1 state for CPU idle which is used while CPU
power down from Linux CPU idle feature. But CPU power down when firmware
send CPU power down request needs new state in self suspend to
distinguish in firmware for CPU power down from power down request or CPU
power down from Linux CPU idle. So add new state PM_STATE_CPU_OFF to
indicate CPU power down from power down request from firmware.
PM_STATE_CPU_OFF state is supported from self-suspend version 3. So
added feature check which sends new state in case of new firmware and
old state i.e. PM_STATE_CPU_IDLE in case of old firmware.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I4118e1b813e5f76fca7b7e9ca1cc598715203fb0
Send subsystem restart notification to firmware when TF-A receives
system reset PSCI call. On receiving subsystem restart call, firmware
will send CPU idle callback to TF-A for powering down all cores. Wait
for CPU idle callback from firmware and raise power down request to
all cores after it receives CPU idle callback to power down core.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I50f417ae228017f38b648740dc90b2e8f1872620
On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ.
By default TF-A uses SGI 6 for CPU power down request. This can be
configurable through CPU_PWRDWN_SGI build flag.
e.g., If user wants to use SGI 7 instead of SGI 6 then provide build
flag CPU_PWRDWN_SGI=7
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd
Currently SGI interrupts are not received in secondary cores because
of issue in GIC configuration. In current Versal NET specific GIC
functions, redistributor configuration is not happening properly.
Because of that SGI interrupt from one processor to another processor
is not transferring. So, use common GIC handlers which will iterate
over all GIC redistributor frames and discovers per cpu redistributor
frame. Also, it initializes corresponding interface in GICv3.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I1433260b8520d6a315fdf5df86bd0688f92d211a
Use generic macro name as per common ARM GIC macro name for Versal
and Versal NET.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2987ff2f612993fc80979f0179c04d316259ed1d
The code in the AMD-Xilinx platform for Versal and Versal NET is being
refactored to move the plat_get_syscnt_freq2() function to a common
file. This common function is utilized for obtaining the CPU clock
frequency from the platform.
Change-Id: I7a4c3fa43a2941d51cacd259c57b24e545aea848
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Refactor, the macro named VERSAL_NET_IOU_SCNTRS is being renamed to a more
generic macro name, which will be used in common code to enable reuse
across various platforms.
Change-Id: I548437e0fe2d73b196468bc92029f8099ea1f8d1
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Refactor the system counter configuration into the
syscnt_freq_config_setup() function as it involves timestamp and
system counter configuration, which requires early configuration for
clock setup and read the value of the IOU_SCNTRS_BASE_FREQ register
using mmio_read_32() to determine the counter frequency.
If the counter frequency is zero, the system will set the default CPU
clocks constants in TF-A and displays message. However, if the counter
frequency is non-zero, the program will return the value stored in the
IOU_SCNTRS_BASE_FREQ register.
The issue lies in dcc_status_timeout(),function verifying timeout
status, particularly within timeout_cnt_us2cnt(), converting
microseconds to counter ticks using read_cntfrq_el0(), which returns
zero. timeout_elapsed() then checks if the current counter from
read_cntpct_el0() exceeds the expiration count, reached to timeout.
After the function set_cnt_freq() writes into the counter frequency
register, the function timeout_cnt_us2cnt() is used to obtain the
appropriate counter ticks. Subsequently, the function timeout_elapsed()
checks whether the current counter value read_cntpct_el0() has
exceeded the specified expiration count. If it has, this indicates
that the timeout has lapsed.
Change-Id: Ib9ed3493d22f23c832f8bb7d11c4f727fe1ebe3c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
There exist inter-processor interrupts on Versal-Net that do not have
corresponding message buffers. These bufferless IPI's on Versal NET
SOC are added to static IPI Tables.
In hardware description there exists two IPI's called 'IPI6' without
buffers that have respective system interrupt values 95 and 101. For
these append the string '_95' or '_101' to denote the difference for
each.
Change-Id: I22bf1a68cb0ed68913eb868f1c197856fc7d82d5
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Reorganize the platform source files necessary across various
Bootloader (BL) configurations within the platform makefile.
This reordering aims to prevent redundant inclusions of these files
across multiple makefiles used for distinct features.
Change-Id: I9c5525dd8522cb8c8e3ad6add70189dcb7cfcc29
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal NET platform. TSP is a component for testing and validating
secure OS and trusted execution environments.
If a BL32 image is present, then there must be a matching Secure-EL1
Payload Dispatcher (SPD) service called TSPD, this service is
responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of BL32
once the runtime services are fully initialized. BL31 invokes such
a registered function to initialize BL32 before running BL33.
The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3 This is
because the S-EL1 can use GIC system registers to manage interrupts
and does not need GIC interface base addresses to be configured.
The secure code load address is initially being pointed to 0x0 in the
handoff parameters, which is different from the default or user-provided
load address of 0x60000000. In this case, set up the PC to the
requested BL32_BASE address to ensure that the secure code is loaded
and executed from the correct location.
Change-Id: I58fe256dc9d6be5cee384c5ebb9baca2737c02a6
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Refactor two platform specific functions, plat_versal_get_mmap() and
plat_versal_net_get_mmap(), to use a more generic function name
plat_get_mmap(). The function can be used in the common code to
obtain memory region.
Change-Id: I3eeb24aff217eef30af60a7742cbebe9d3b2edce
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
