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fix(xilinx): rename macros to align with ARM

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Use generic macro name as per common ARM GIC macro name for Versal
and Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2987ff2f612993fc80979f0179c04d316259ed1d
This commit is contained in:
Jay Buddhabhatti 2023-10-05 05:21:50 -07:00
parent 2b6f940a10
commit 79953190bc
7 changed files with 18 additions and 18 deletions
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2
plat/xilinx/common/pm_service/pm_api_sys.c
View file

@ -50,7 +50,7 @@ void pm_client_set_wakeup_sources(uint32_t node_id)
{
uint32_t reg_num, device_id;
uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX] = {0U};
uint32_t isenabler1 = PLAT_GICD_BASE_VALUE + GICD_ISENABLER + 4U;
uint32_t isenabler1 = PLAT_ARM_GICD_BASE + GICD_ISENABLER + 4U;
zeromem(&pm_wakeup_nodes_set, (u_register_t)sizeof(pm_wakeup_nodes_set));

4
plat/xilinx/versal/include/plat_macros.S
View file

@ -103,8 +103,8 @@ exit_print_gic_regs:
* ---------------------------------------------
*/
.macro plat_crash_print_regs
mov_imm x17, PLAT_GICD_BASE_VALUE
mov_imm x16, PLAT_GICR_BASE_VALUE
mov_imm x17, PLAT_ARM_GICD_BASE
mov_imm x16, PLAT_ARM_GICR_BASE
versal_print_gic_regs
.endm

4
plat/xilinx/versal/include/platform_def.h
View file

@ -103,8 +103,8 @@
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#define PLAT_GICD_BASE_VALUE U(0xF9000000)
#define PLAT_GICR_BASE_VALUE U(0xF9080000)
#define PLAT_ARM_GICD_BASE U(0xF9000000)
#define PLAT_ARM_GICR_BASE U(0xF9080000)
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3

4
plat/xilinx/versal/versal_gicv3.c
View file

@ -62,8 +62,8 @@ static uint32_t versal_gicv3_mpidr_hash(u_register_t mpidr)
}
static const gicv3_driver_data_t versal_gic_data __unused = {
.gicd_base = PLAT_GICD_BASE_VALUE,
.gicr_base = PLAT_GICR_BASE_VALUE,
.gicd_base = PLAT_ARM_GICD_BASE,
.gicr_base = PLAT_ARM_GICR_BASE,
.interrupt_props = versal_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(versal_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,

4
plat/xilinx/versal_net/include/plat_macros.S
View file

@ -109,8 +109,8 @@ exit_print_gic_regs:
* Uncomment it when versions are stable
*/
/*
mov_imm x17, PLAT_GICD_BASE_VALUE
mov_imm x16, PLAT_GICR_BASE_VALUE
mov_imm x17, PLAT_ARM_GICD_BASE
mov_imm x16, PLAT_ARM_GICR_BASE
versal_net_print_gic_regs
*/
.endm

10
plat/xilinx/versal_net/include/platform_def.h
View file

@ -107,8 +107,8 @@
#define CACHE_WRITEBACK_SHIFT U(6)
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#define PLAT_GICD_BASE_VALUE U(0xE2000000)
#define PLAT_GICR_BASE_VALUE U(0xE2060000)
#define PLAT_ARM_GICD_BASE U(0xE2000000)
#define PLAT_ARM_GICR_BASE U(0xE2060000)
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
@ -118,13 +118,13 @@
#define PLAT_VERSAL_NET_IPI_IRQ 89
#define PLAT_VERSAL_IPI_IRQ PLAT_VERSAL_NET_IPI_IRQ
#define PLAT_VERSAL_NET_G1S_IRQ_PROPS(grp) \
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL)
#define PLAT_VERSAL_NET_G0_IRQ_PROPS(grp) \
#define PLAT_ARM_G0_IRQ_PROPS(grp) \
INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
GIC_INTR_CFG_EDGE)
#define IRQ_MAX 200U

8
plat/xilinx/versal_net/versal_net_gicv3.c
View file

@ -31,8 +31,8 @@
static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
static const interrupt_prop_t versal_net_interrupt_props[] = {
PLAT_VERSAL_NET_G1S_IRQ_PROPS(INTR_GROUP1S),
PLAT_VERSAL_NET_G0_IRQ_PROPS(INTR_GROUP0)
PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
};
/*
@ -63,8 +63,8 @@ static uint32_t versal_net_gicv3_mpidr_hash(u_register_t mpidr)
}
static const gicv3_driver_data_t versal_net_gic_data __unused = {
.gicd_base = PLAT_GICD_BASE_VALUE,
.gicr_base = PLAT_GICR_BASE_VALUE,
.gicd_base = PLAT_ARM_GICD_BASE,
.gicr_base = PLAT_ARM_GICR_BASE,
.interrupt_props = versal_net_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(versal_net_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,