Stephan Gerhold c5c160cddd fix(cpus): flush L2 cache for Cortex-A7/12/15/17 ... Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an (optional) integrated L2 cache that might need to be flushed if the whole cluster is powered down. However, unlike Cortex-A53 there is currently no L2 cache flush in the cluster_pwr_dwn implementation for some reason. This causes problems if there is unwritten data left in the L2 cache during a cluster power off. Fix this by adding the L2 cache flush similar to cortex_a53.S. Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>		2023-08-10 09:28:52 +02:00
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aarch32	fix(cpus): flush L2 cache for Cortex-A7/12/15/17	2023-08-10 09:28:52 +02:00
aarch64	Merge "fix(cpus): revert erroneous use of override_vector_table macro in Cortex-A73" into integration	2023-08-08 22:33:45 +02:00
cpu-ops.mk	fix(cpus): workaround for Neoverse N2 erratum 2779511	2023-08-03 22:42:31 +02:00
errata_report.c	fix(cpus): reduce generic_errata_report()'s size	2023-06-15 10:14:59 +01:00