Stephan Gerhold c5c160cddd fix(cpus): flush L2 cache for Cortex-A7/12/15/17 ... Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an (optional) integrated L2 cache that might need to be flushed if the whole cluster is powered down. However, unlike Cortex-A53 there is currently no L2 cache flush in the cluster_pwr_dwn implementation for some reason. This causes problems if there is unwritten data left in the L2 cache during a cluster power off. Fix this by adding the L2 cache flush similar to cortex_a53.S. Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>		2023-08-10 09:28:52 +02:00
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aem_generic.S	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00
cortex_a5.S	refactor(cpus): convert the Cortex-A5 to use the errata framework	2023-08-04 11:34:28 -05:00
cortex_a7.S	fix(cpus): flush L2 cache for Cortex-A7/12/15/17	2023-08-10 09:28:52 +02:00
cortex_a9.S	refactor(cpus): use cpu errata wrappers Cortex-A7 and A9 aarch32 cpus	2023-08-03 14:07:01 -05:00
cortex_a12.S	fix(cpus): flush L2 cache for Cortex-A7/12/15/17	2023-08-10 09:28:52 +02:00
cortex_a15.S	fix(cpus): flush L2 cache for Cortex-A7/12/15/17	2023-08-10 09:28:52 +02:00
cortex_a17.S	fix(cpus): flush L2 cache for Cortex-A7/12/15/17	2023-08-10 09:28:52 +02:00
cortex_a32.S	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00
cortex_a53.S	refactor(cpus): add Cortex-A53 errata framework information	2023-07-27 09:35:12 +01:00
cortex_a57.S	fix(security): report CVE 2022 23960 missing for aarch32 A57 and A72	2022-05-05 18:38:38 +02:00
cortex_a72.S	refactor(cpus): add Cortex-A72 errata information	2023-06-27 15:42:21 +01:00
cpu_helpers.S	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00