Maheedhar Bollapalli 5cb9125e96 fix(versal2): update transfer list as optional ... Updated transfer list feature as optional and user should explicitly provide build time argument to enable transfer list. In TL optional case TL address range is utilized as default dtb address range. Updated default DT address to transfer list address. Change-Id: Ieeaacb3e6fda4ad1da9330708e19d776bffb06c1 Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>		2025-02-17 06:10:55 +00:00
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aarch64	feat(versal2): update platform version to versal2	2025-01-24 14:59:33 +05:30
include	Merge "fix(versal2): update DDR address map" into integration	2025-02-06 09:27:45 +01:00
tsp	feat(versal2): add support for AMD Versal Gen 2 platform	2024-06-10 08:09:49 +02:00
bl31_setup.c	feat(versal2): update platform version to versal2	2025-01-24 14:59:33 +05:30
gicv3.c	feat(versal2): add support for AMD Versal Gen 2 platform	2024-06-10 08:09:49 +02:00
plat_psci.c	fix(versal2): modify function to have single return	2025-01-22 04:07:35 +00:00
plat_topology.c	fix(versal2): modify function to have single return	2025-01-22 04:07:35 +00:00
platform.mk	fix(versal2): update transfer list as optional	2025-02-17 06:10:55 +00:00
scmi.c	fix(versal2): modify function to have single return	2025-01-22 04:07:35 +00:00
sip_svc_setup.c	fix(versal2): typecast expressions to match data type	2024-12-20 11:01:09 +00:00
soc_ipi.c	feat(versal2): add support for AMD Versal Gen 2 platform	2024-06-10 08:09:49 +02:00