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fix(versal2): update transfer list as optional

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Updated transfer list feature as optional and user should explicitly
provide build time argument to enable transfer list.
In TL optional case TL address range is utilized as default dtb
address range. Updated default DT address to transfer list address.

Change-Id: Ieeaacb3e6fda4ad1da9330708e19d776bffb06c1
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This commit is contained in:
Maheedhar Bollapalli 2025-01-23 08:36:57 +00:00
parent 5e941e78e0
commit 5cb9125e96
1 changed files with 4 additions and 4 deletions
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8
plat/amd/versal2/platform.mk
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@ -1,6 +1,6 @@
# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@ -86,8 +86,8 @@ else
endif
endif
ifdef XILINX_OF_BOARD_DTB_ADDR
ifeq (${TRANSFER_LIST},0)
XILINX_OF_BOARD_DTB_ADDR ?= 0x1000000
$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
endif
@ -153,7 +153,7 @@ $(eval $(call add_define, CORTEX_A78_AE_H_INC))
endif
# Enable Handoff protocol using transfer lists
TRANSFER_LIST := 1
TRANSFER_LIST ?= 0
include lib/transfer_list/transfer_list.mk
BL31_SOURCES += plat/xilinx/common/plat_xfer_list.c