Marcin Wojtas 4acd900df6 gicv2: enable configuring IRQ trigger type ... This patch introduces new helper routines that allow configuring the individual IRQs to be edge/level-triggered via GICD_ICFGR registers. This is helpful to modify the default configuration of the non-secure GIC SPI's, which are all set during initialization to be level-sensitive. Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>		2018-09-03 15:46:14 +03:00
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common	GIC: Fix setting interrupt configuration	2018-03-26 09:45:48 +01:00
v2	gicv2: enable configuring IRQ trigger type	2018-09-03 15:46:14 +03:00
v3	GIC: Do not flush cache when unneeded	2018-07-26 14:14:07 -05:00
arm_gic.c	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
gic_v2.c	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
gic_v3.c	Fix pointer type mismatch of handlers	2018-04-27 18:35:02 +09:00