Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-25 22:35:42 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

gicv2: enable configuring IRQ trigger type

Browse source 
This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful to modify
the default configuration of the non-secure GIC SPI's, which
are all set during initialization to be level-sensitive.

Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
This commit is contained in:
Marcin Wojtas 2018-03-21 09:55:47 +01:00 • committed by Konstantin Porotchkin
parent 155d01ff1e
commit 4acd900df6
2 changed files with 10 additions and 0 deletions
drivers/arm/gic/v2
gicv2_main.c
include/drivers/arm
gicv2.h

9
drivers/arm/gic/v2/gicv2_main.c
View file

@ -593,3 +593,12 @@ unsigned int gicv2_set_pmr(unsigned int mask)
return old_mask;
}
/*******************************************************************************
* This function updates single interrupt configuration to be level/edge
* triggered
******************************************************************************/
void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg)
{
gicd_set_icfgr(driver_data->gicd_base, id, cfg);
}

1
include/drivers/arm/gicv2.h
View file

@ -191,6 +191,7 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num);
void gicv2_set_interrupt_pending(unsigned int id);
void gicv2_clear_interrupt_pending(unsigned int id);
unsigned int gicv2_set_pmr(unsigned int mask);
void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
#endif /* __ASSEMBLY__ */
#endif /* __GICV2_H__ */