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GIC: Do not flush cache when unneeded
When a platform enables its caches before it initializes the GICC/GICR interface then explicit cache maintenance is not needed. Remove these here. Signed-off-by: Andrew F. Davis <afd@ti.com>
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2 changed files with 7 additions and 5 deletions
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@ -221,9 +221,10 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
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* enabled. When the secondary CPU boots up, it initializes the
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* GICC/GICR interface with the caches disabled. Hence flush the
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* driver_data to ensure coherency. This is not required if the
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* platform has HW_ASSISTED_COHERENCY enabled.
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* platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
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* enabled.
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*/
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#if !HW_ASSISTED_COHERENCY
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#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
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flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data));
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flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data));
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#endif
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@ -360,7 +361,7 @@ void gicv2_set_pe_target_mask(unsigned int proc_num)
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if (driver_data->target_masks[proc_num] == 0) {
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driver_data->target_masks[proc_num] =
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gicv2_get_cpuif_id(driver_data->gicd_base);
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#if !HW_ASSISTED_COHERENCY
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#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
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/*
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* PEs only update their own masks. Primary updates it with
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* caches on. But because secondaries does it with caches off,
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@ -147,9 +147,10 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
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* enabled. When the secondary CPU boots up, it initializes the
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* GICC/GICR interface with the caches disabled. Hence flush the
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* driver data to ensure coherency. This is not required if the
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* platform has HW_ASSISTED_COHERENCY enabled.
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* platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
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* enabled.
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*/
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#if !HW_ASSISTED_COHERENCY
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#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
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flush_dcache_range((uintptr_t) &gicv3_driver_data,
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sizeof(gicv3_driver_data));
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flush_dcache_range((uintptr_t) gicv3_driver_data,
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