Marcin Wojtas 4acd900df6 gicv2: enable configuring IRQ trigger type ... This patch introduces new helper routines that allow configuring the individual IRQs to be edge/level-triggered via GICD_ICFGR registers. This is helpful to modify the default configuration of the non-secure GIC SPI's, which are all set during initialization to be level-sensitive. Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>		2018-09-03 15:46:14 +03:00
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cci	cci: Use dsb to wait before reading status register	2018-08-13 14:20:30 +01:00
cci400	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
ccn	Fix type of unsigned long constants	2017-09-21 12:03:53 +01:00
gic	gicv2: enable configuring IRQ trigger type	2018-09-03 15:46:14 +03:00
pl011	[PATCH 1/2] qemu: Support MULTI_CONSOLE_API	2018-03-05 20:14:39 +08:00
pl061	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
smmu	Fix MISRA Rule 5.3 Part 2	2018-06-12 13:21:36 +01:00
sp804	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
sp805	Fix MISRA defects in SP805 driver	2018-07-30 09:30:15 +01:00
tzc	Fix MISRA Rule 5.3 Part 2	2018-06-12 13:21:36 +01:00
tzc400	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00