Jayanth Dodderi Chidanand 7623e085cb feat(cm): test integrity of el1_ctx registers ... * This patch adds support to tsp (BL32) Image, to exercise EL1_context registers at S-EL1. * Adds a SMC function ID "MODIFY_EL1_CTX" to handle EL1_CTX registers at S-EL1 and overwrite them. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: Id4f2b3b748f7bc9e6c9d72a2f03d50aefbfb61cb		2024-11-08 11:05:13 +00:00
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arch	Merge "build(bl31): support separated memory for RW DATA" into integration	2024-11-07 18:10:51 +01:00
bl1	refactor(bl1): clean up bl2 layout calculation	2024-04-26 09:00:12 +00:00
bl2
bl2u
bl31	Merge "refactor(sdei): use common create_spsr() in SDEI library" into integration	2024-03-14 21:17:45 +01:00
bl32	feat(cm): test integrity of el1_ctx registers	2024-11-08 11:05:13 +00:00
common	feat(d128): add support for FEAT_D128	2024-10-24 14:51:55 -05:00
drivers	fix(intel): refactor SDMMC driver for Altera products	2024-10-25 09:38:51 +08:00
dt-bindings	fix(dt-bindings): update STM32MP2 clock and reset bindings	2024-06-27 17:17:35 +02:00
export	feat(tbbr): add image id for backup GPT	2023-10-27 08:31:54 -05:00
lib	feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA	2024-11-06 16:52:12 +01:00
plat	feat(rmmd): el3 token sign during attestation	2024-10-15 08:20:28 -07:00
services	feat(rmmd): el3 token sign during attestation	2024-10-15 08:20:28 -07:00
tools_share	fix(tc): add SCP_BL2 to RSE measured boot	2024-06-13 15:53:10 +02:00