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3f9df2c6ad
Cortex-X3 erratum 2302506 is a cat B erratum that applies to revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidation to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN can be found here: https://developer.arm.com/documentation/2055130/latest Change-Id: I048b830867915b88afa36582c6da05734a56d22a Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> |
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| .. | ||
| _static/css | ||
| about | ||
| components | ||
| design | ||
| design_documents | ||
| getting_started | ||
| perf | ||
| plat | ||
| process | ||
| resources | ||
| security_advisories | ||
| threat_model | ||
| tools | ||
| change-log.md | ||
| conf.py | ||
| global_substitutions.txt | ||
| glossary.rst | ||
| index.rst | ||
| license.rst | ||
| Makefile | ||
| porting-guide.rst | ||