Bipin Ravi 3f9df2c6ad fix(cpus): workaround for Cortex-X3 erratum 2302506 ... Cortex-X3 erratum 2302506 is a cat B erratum that applies to revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidation to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN can be found here: https://developer.arm.com/documentation/2055130/latest Change-Id: I048b830867915b88afa36582c6da05734a56d22a Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>		2024-01-17 14:22:21 -06:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	fix(docs): revise the description of REGISTER_CRYPTO_LIB	2023-11-29 14:39:31 +08:00
cpu-specific-build-macros.rst	fix(cpus): workaround for Cortex-X3 erratum 2302506	2024-01-17 14:22:21 -06:00
firmware-design.rst	feat(docs): save BL32 image base and size in entry point info	2023-11-07 10:36:53 +00:00
index.rst	docs: add top level section numbering	2022-11-16 14:06:48 +00:00
interrupt-framework-design.rst	Fix broken links to various sections across docs	2020-08-03 09:55:04 -05:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	docs: update RESET_TO_BL31 documentation	2023-03-09 14:42:49 +00:00
trusted-board-boot-build.rst	docs(arm): add ARM_ROTPK_LOCATION variant full key	2022-12-09 14:55:39 -06:00
trusted-board-boot.rst	feat(cert-create): add pkcs11 engine support	2023-09-21 13:27:25 +02:00