Commit graph

2472 commits

Author SHA1 Message Date
Elizabeth Ho
7bbccd4de6 docs: remove blank pages from PDF documentation
The PDF documentation download has a lot of blank pages. This is
because Sphinx starts each section on an odd numbered page for
duplex printing. This patch fixes this to allow sections to start
on any page.

Change-Id: I1ba8a4707c39b54205f2a3c9b47c1c21a3fedcb9
Signed-off-by: Elizabeth Ho <elizabeth.ho@arm.com>
2023-08-02 14:22:59 +01:00
Shruti Gupta
b175287075 docs(rme): update tftf build command
Deprecate pack_realm build command for TFTF.
To build Realm payload tests use ENABLE_REALM_PAYLOAD_TESTS=1.
This new command line for TFTF is effective from SHA 9945bef6b
in tf-a-tests repo.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: Iee9ac9b2b367aac50677fac95631e7e4818cdf3a
2023-08-02 13:31:10 +01:00
laurenw-arm
5b00658867 docs(psa): doc AP/RSS interfaces for NV ctrs/ROTPK
Adding documentation for AP/RSS interfaces for NV counters and ROTPK

Change-Id: I38745bcc5d53317bab07bb81f11f9ba4551a224f
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2023-07-31 10:49:05 -05:00
Harrison Mutai
c365476003 fix: use rsvg-convert as the conversion backend
The auxiliary pdf build requires SVG files to be converted to pdf files.
Use libRSVG as a light weight alternative to inkscape, and ensure it's
installed in the build environment.

Change-Id: I1fdb05fb2701fc28a04e210d5928f4387ca08613
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-07-28 12:37:49 +01:00
Manish V Badarkhe
137d934dd9 docs(rss): update RSS doc for signer-ID
Added details about the API that calculates the signer-ID and updated
console log details to provide signer-ID information for each image.

Change-Id: If637b3719418e9c0b8d2844c92bddbdfe454bfb8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-07-28 09:01:15 +01:00
Manish V Badarkhe
97653189bc docs: add details about plat_mboot_measure_key function
Added details of 'plat_mboot_measure_key' function in the porting-guide.

Change-Id: Id62211abc0ba13a0f581dc8e24c7b367afe2dcf5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-07-28 09:01:04 +01:00
rutigl@gmail.com
edcece15c7 feat(nuvoton): added support for npcm845x chip
Initial version

Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Change-Id: If433d325a90b519ae5f02411865bffd368ff2824
2023-07-26 08:14:45 +03:00
Manish V Badarkhe
43a6544f01 Merge "chore(docs): update march utility details" into integration 2023-07-25 16:53:26 +02:00
Moritz Fischer
40c81ed533 fix(cpus): workaround for Neoverse V2 erratum 2801372
Neoverse V2 erratum 2801372 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.

This errata is explained in SDEN 2332927 available at:
https://developer.arm.com/documentation/SDEN2332927

Change-Id: I8716b9785a67270a72ae329dc49a2f2239dfabff
Signed-off-by: Moritz Fischer <moritzf@google.com>
2023-07-21 16:52:36 +02:00
Manish V Badarkhe
e755d005d0 Merge "docs(maintainers): update AMD maintainers list" into integration 2023-07-20 12:43:48 +02:00
Akshay Belsare
bc5aceeb00 docs(maintainers): update AMD maintainers list
Maintainers for AMD platform ports has been updated.
"Amit Nagal" and "Akshay Belsare" are added to the list.

Change-Id: Ia64e1ec6c2f80515054730d307d41b0060d3dcc7
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
2023-07-20 14:58:50 +05:30
Maksims Svecovs
4d0b66323b feat(mte): adds feature detection for MTE_PERM
Adds feature detection for v8.9 feature FEAT_MTE_PERM. Adds respective
ID_AA64PFR2_EL1 definitions and ENABLE_FEAT_MTE_PERM define.

Change-Id: If24b42f1207154e639016b0b840b2d91c6ee13d4
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-07-20 09:00:22 +01:00
Govindraj Raja
019311e712 chore(docs): update march utility details
commit@7794d6c8f8c44acc14fbdc5ada5965310056be1e added a march utility
but the details were not updated in docs.

Update docs to provide a glimpse of march utility added.

Change-Id: I696cb9a701a30d7bf36a1ecd38a80d07df1fd551
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-07-19 09:43:06 -05:00
Stephan Gerhold
c97c7ebfec docs(msm8916): document new platforms
Document the new platform build options for the MSM8916 port which now
supports multiple similar Qualcomm SoCs:

  - Snapdragon 410 (PLAT=msm8916) as before
  - Snapdragon 615 (PLAT=msm8939)
  - Snapdragon 210 (PLAT=msm8909)
  - Snapdragon X5 Modem (PLAT=mdm9607)

The latter two use AArch32-only ARM Cortex-A7 cores that only support
using BL32/SP_MIN and not BL31 on AArch64.

Change-Id: I9fffe60dd0ad2acc18f006f11e91854b9e8dcb8f
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-07-19 12:56:08 +02:00
Manish Pandey
5dbb812ebd Merge "docs: move common build option from Arm-specific to common file" into integration 2023-07-17 15:48:20 +02:00
Manish V Badarkhe
6e26ffc02a Merge "docs(morello): update the boot sequence according to the TBBR boot flow" into integration 2023-07-11 18:12:18 +02:00
Deepthi Peter
13fc020d1b docs(morello): update the boot sequence according to the TBBR boot flow
The boot sequence mentioned in the documentation referred to an older
boot flow. This patch updates the boot sequence to the TBBR boot flow
that is currently being followed.

Signed-off-by: Deepthi Peter <deepthi.peter@arm.com>
Change-Id: I183458cea6d43dcf8acba2e0422920ab5541fdfc
2023-07-11 10:44:46 +05:30
Manish Pandey
49c7a26419 Merge changes from topic "mb/mb-design" into integration
* changes:
  docs: remove redundant Measured Boot interface info
  docs: add Measured Boot design
2023-07-10 14:03:12 +02:00
Olivier Deprez
e318411f02 Merge "docs: add guidelines for abandoning patches" into integration 2023-07-07 12:10:48 +02:00
Manish V Badarkhe
a1c93550bc docs: remove redundant Measured Boot interface info
A separate design document for Measured Boot covers the porting
guidelines for the Measured Boot interfaces. As a result,
the Measured Boot interfaces have been removed from the porting
guide and a link to the Measured Boot design document has been
provided.

Change-Id: Ia6bd2620d830aea6aececab4af7e10a6d737f025
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-07-06 12:14:38 +01:00
Manish V Badarkhe
5038f1f90e docs: add Measured Boot design
Added design document for Measured Boot implementation in
TF-A.

Change-Id: I25b57ec555b289eb6bbf0a6aae014d7bf6d152fd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-07-06 12:14:30 +01:00
Manish V Badarkhe
8671000ff7 docs: add guidelines for abandoning patches
The code review guidelines have been updated to explain when
patches that do not receive a response to the review comments
will be abandoned.

Change-Id: I60539e16ca41245cf1b352f24557be1b3c67c367
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-07-06 11:20:28 +01:00
Jacky Bai
c190f3ed6c docs(maintainers): add maintainers for i.MX9 SoCs
Add maintainers for NXP i.MX9 SoC family.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I6dd694af56da9f4d241fda28b781254586b5f462
2023-06-30 10:24:05 +08:00
Jacky Bai
c472b7502e docs(imx9): add imx93 platform
Add i.MX9 platform introduction.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic07ca394cff6a9e3e21b7a03f9c9080d3c1ef91a
2023-06-30 10:24:05 +08:00
Madhukar Pappireddy
e87102f32b Merge changes from topic "gr/cpu_rename" into integration
* changes:
  chore: rename hayes to a520
  chore: rename hunter to a720
  chore: rename hunter_elp to cortex-x4
2023-06-29 17:36:44 +02:00
Govindraj Raja
dea3d71e9a chore: rename hayes to a520
Rename Cortex-hayes to Cortes-A520

Change-Id: Ic574b55b1aaf11b5bf7b583e244245e7b54bdb22
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-06-29 17:20:17 +02:00
Govindraj Raja
31b3945527 chore: rename hunter to a720
Rename cortex_hunter to cortex_a720

Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-06-29 16:20:01 +01:00
Boyan Karatotev
83a4dae1af refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init
The FEAT_MTPMU feature disable runs very early after reset. This means,
it needs to be written in assembly, since the C runtime has not been
initialised yet.

However, there is no need for it to be initialised so soon. The PMU
state is only relevant after TF-A has relinquished control. The code
to do this is also very verbose and difficult to read. Delaying the
initialisation allows for it to happen with the rest of the PMU. Align
with FEAT_STATE in the process.

BREAKING CHANGE: This patch explicitly breaks the EL2 entry path. It is
currently unsupported.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2aa659d026fbdb75152469f6d19812ece3488c6f
2023-06-29 09:59:06 +01:00
Olivier Deprez
448d4d97aa Merge "docs: remove deprecated tc0 from list of supported FVPs" into integration 2023-06-28 15:44:31 +02:00
Manish V Badarkhe
acd03f4b75 docs: move common build option from Arm-specific to common file
Moved common build options from Arm-specific file to common build
file.

Change-Id: If74b6223972ae3a6c11d9f9d2fbd8d2ee008b6e5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-06-27 12:47:28 +01:00
Manish Pandey
3995f30c55 Merge "refactor(build): merge march32/64 directives" into integration 2023-06-27 10:19:56 +02:00
Manish V Badarkhe
059b19bd44 Merge "docs: move the Juno-specific build option to Arm build option file" into integration 2023-06-23 16:01:50 +02:00
Manish V Badarkhe
e8947b27fe Merge "feat(fvp): allow configurable FVP Trusted SRAM size" into integration 2023-06-23 16:01:09 +02:00
Daniel Boulby
fa07049ee7 docs: remove deprecated tc0 from list of supported FVPs
TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Id013fcecbe20700611463ef9eab8cb3ae09071cc
2023-06-23 11:46:06 +01:00
Govindraj Raja
d4089fb8d8 refactor(build): merge march32/64 directives
Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.

Merge this two separate directives to a common one as march-directive.

Change-Id: I220d2b782eb3b54e13ffd5b6a581d0e6da68756a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-06-22 16:37:03 -05:00
Manish V Badarkhe
31df063281 docs: move the Juno-specific build option to Arm build option file
Moved the Juno-specific build option from the common build option
file to the Arm build option file.

Change-Id: I0f53203f0cfca4a3baadab2cee4339c9694cfe8b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-06-22 16:00:32 +02:00
Chris Kay
41e56f422d feat(fvp): allow configurable FVP Trusted SRAM size
In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you to configure a larger Trusted SRAM of 512KB.

This change introduces the `FVP_TRUSTED_SRAM_SIZE` build option, which
allows you to explicitly specify how much of the Trusted SRAM to
utilise, e.g.:

    FVP_TRUSTED_SRAM_SIZE=384

This allows previously-failing configurations to build successfully by
utilising more than the originally-allocated 256KB of the Trusted SRAM
while maintaining compatibility with older configurations/models that
only require/have 256KB.

Change-Id: I8344d3718564cd2bd53f1e6860e2fe341ae240b0
Signed-off-by: Chris Kay <chris.kay@arm.com>
2023-06-21 14:16:11 +02:00
Stephan Gerhold
b4e49e3fe4 docs(msm8916): document new build options
Update the MSM8916 platform documentation with the new build options
introduced in the previous changes:

  - AArch32 (BL32/SP_MIN)
  - UART selection

While at it, also document the build options that allow changing the
memory addresses (PRELOADED_BL33_BASE, BL31_BASE, BL32_BASE).

Change-Id: I2370c8264982317693f69fda0b03a255f12bafe2
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-06-20 18:52:53 +02:00
Manish Pandey
bf1e58e737 Merge "docs: update PSCI reference" into integration 2023-06-16 10:44:39 +02:00
Lauren Wehrmeister
aa1055e300 Merge "fix(cpus): reduce generic_errata_report()'s size" into integration 2023-06-15 19:07:36 +02:00
Lauren Wehrmeister
d2e0743698 Merge changes from topic "bk/errata_refactor" into integration
* changes:
  feat(cpus): add more errata framework helpers
  docs: document the errata framework
2023-06-15 16:28:41 +02:00
Boyan Karatotev
f43e09a12e fix(cpus): reduce generic_errata_report()'s size
For a pretty implementation and straightforward code, the CVE/erratum
dispatching of the errata status reporting was done with a macro,
closely following the old code. Unfortunately, this produces a function
that was over a kilobyte in size, which unsurprisingly doesn't fit on
some platforms.

Convert the macro to a proper C function and call it once. Also hide the
errata ordering checking behind the FEATURE_DETECTION flag to further
save space. This functionality is not necessary for most builds.
Development and platform bringup builds, which should find this
functionality useful, are expected to have FEATURE_DETECTION enabled.

This reduces the function to under 600 bytes.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibf5376a26cbae28d9dc010128452cb3c694a3f78
2023-06-15 10:14:59 +01:00
Boyan Karatotev
6a0e8e80fb docs: document the errata framework
Also add a recommended Procedure Call Standard (PCS) to use inside CPU
files and split everything into sections to make it easier to follow.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Idd876d8e598b5dfe1193aa3e7375c52f6edf5671
2023-06-15 10:14:58 +01:00
Manish V Badarkhe
032c698350 Merge "feat(ast2700): add Aspeed AST2700 platform support" into integration 2023-06-15 10:57:58 +02:00
Manish V Badarkhe
3be6b4fbe5 docs: update PSCI reference
PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.

Change-Id: I35ee365f08c557f3017af4d51f6d063a7501b27e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-06-15 09:46:43 +01:00
Lauren Wehrmeister
0484b2cb9c Merge "docs: update Measured Boot PoC" into integration 2023-06-12 18:23:37 +02:00
Sandrine Bailleux
7ae96dcebd Merge "chore(bl): add UNALIGNED symbols for TEXT/RODATA" into integration 2023-06-12 14:43:17 +02:00
Manish V Badarkhe
7a8a97f582 Merge changes from topics "hm/latex", "hm/latexpdf" into integration
* changes:
  fix(docs): fix build errors for latexpdf
  chore: reformat sphinx configuration
2023-06-12 13:49:19 +02:00
Michal Simek
f7d445fcbb chore(bl): add UNALIGNED symbols for TEXT/RODATA
Add symbols to mark end of TEXT/RODATA before page alignment.
Similar change was done by commit 8d69a03f6a ("Various
improvements/cleanups on the linker scripts") for
RO_END/COHERENT_RAM. These symbols help to know how much free
space is in the final binary because of page alignment.

Also show all *UNALIGNED__ symbols via poetry.
For example:
poetry run memory -p zynqmp -b debug

Change-Id: I322beba37dad76be9f4e88ca7e5b3eff2df7d96e
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12 12:50:08 +02:00
Harrison Mutai
443d6ea699 fix(docs): fix build errors for latexpdf
Fixes errors encountered when handling SVG graphics, unicode characters,
and deeply nested lists (i.e. in the change log) with the `latexpdf`
docs build. Adds `sphinxcontrib-svg2pdfconverter` to allow embedding SVG
images into PDF files; changes the LaTeX engine to XeLaTex to provide
wider support for unicode characters (see [1] for more details); and
increases the maximum list depth.

[1] https://www.sphinx-doc.org/en/master/usage/configuration.html#confval-latex_engine

Change-Id: I2ee265d301f6822bae7aa6dfa3a8bfcf070076d3
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-06-12 10:56:30 +01:00