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docs(morello): update the boot sequence according to the TBBR boot flow

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The boot sequence mentioned in the documentation referred to an older
boot flow. This patch updates the boot sequence to the TBBR boot flow
that is currently being followed.

Signed-off-by: Deepthi Peter <deepthi.peter@arm.com>
Change-Id: I183458cea6d43dcf8acba2e0422920ab5541fdfc
This commit is contained in:
Deepthi Peter 2023-07-03 09:03:22 +05:30
parent e318411f02
commit 13fc020d1b
1 changed files with 14 additions and 4 deletions
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18
docs/plat/arm/morello/index.rst
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@ -12,9 +12,19 @@ Further information on Morello Platform is available at `info <https://developer
Boot Sequence
-------------
The execution begins from SCP_BL1 which loads the SCP_BL2 and starts its
execution. SCP_BL2 powers up the AP which starts execution at AP_BL31. The AP
then continues executing and hands off execution to Non-secure world (UEFI).
The SCP initializes the RVBAR registers to point to the AP_BL1. Once RVBAR is
initialized, the primary core is powered on. The primary core boots the AP_BL1.
It performs minimum initialization necessary to load and authenticate the AP
firmware image (the FIP image) from the AP QSPI NOR Flash Memory into the
Trusted SRAM.
AP_BL1 authenticates and loads the AP_BL2 image. AP_BL2 performs additional
initializations, and then authenticates and loads the AP_BL31 and AP_BL33.
AP_BL2 then transfers execution control to AP_BL31, which is the EL3 runtime
firmware. Execution is finally handed off to AP_BL33, which is the non-secure
world (UEFI).
SCP -> AP_BL1 -> AP_BL2 -> AP_BL31 -> AP_BL33
Build Procedure (TF-A only)
~~~~~~~~~~~~~~~~~~~~~~~~~~~
@ -30,4 +40,4 @@ Build Procedure (TF-A only)
make PLAT=morello all
*Copyright (c) 2020, Arm Limited. All rights reserved.*
*Copyright (c) 2020-2023, Arm Limited. All rights reserved.*