The Yocto team has requested that we do not use Poetry from within the
Makefile, as Yocto does not have network access during the build
process.
We want to maintain the current behaviour, so this change makes our use
of Poetry contigent on it being available in the environment.
Additionally, explicitly passing an empty toolchain parameter now allows
a tool to be *disabled* (e.g. passing `POETRY=` will prevent the build
system from trying to use Poetry).
Change-Id: Ibf552a3fee1eaadee767a1b948b559700083b401
Signed-off-by: Chris Kay <chris.kay@arm.com>
Cortex-X4 erratum 2897503 is a Cat B erratum that applies
to all revisions <= r0p1 and is fixed in r0p2.
The workaround is to set CPUACTLR4_EL1[8] to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3178a890b6f1307b310e817af75f8fdfb8668cc9
During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the sync-up of stale
values in the cache to be synced with the main memory.
So, before the cache cleaning is done in u-boot proper,
it is invalidated in BL31 so that the cache data gets in
sync with u-boot proper memory address space and when
u-boot proper does its initialization which in turn clears
its BSS and heap section.
Change-Id: Ic8d8672f1e371868be7f54f5a1fae9229ab15164
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Increase the timeout of waiting for bridge ack to solve the
fpga config hung.
Change-Id: I967af02b336c296206b4947be718953ff8ca30cf
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change the size of BL31 limit allocation to be half the sysram size.
Defining BL31_PROGBITS_LIMIT to detect overflows.
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iccc1cc0826b8113a3c2fd6ffa77ca419795854d3
It will be used for PMIC on STM32MP257F-EV board.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7f95220512de4416323b381fec7c7dcb044c64fd
Update stm32mp251.dtsi SoC DT file to include UART and I2C nodes.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I6f52ec2c1735d28ba4a424af71e7eae5b0ac3e0d
The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boot of a board.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ibe0cacf8aec2871eb9a86ec16cbbd18d3745fe9e
Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent clocks in the clock tree. Therefore, enabling the A53 clock
will also turn on the A53 PLL and the oscillator that feeds it.
Change-Id: Ifc2bee3e9edbb4baced34f9e809a961562f7d0a6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type. Usually, this is determined based on the parent
field, but not always.
Change-Id: I76a3d2636dc23ba2d547d058b8650dd0e99fe1fa
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The UART clock initialization failed because the clock mux enablement
mechanism did not correctly recognize the PERIPH PLL mux. Therefore, it
was reported as an unknown mux ID.
Change-Id: I6cc72c87a8462a2ed2e7c360f59a74961bb2f3a1
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up integration of TLC into the build system.
Change-Id: I4466e27a457dfd5bf709dc3a360a2b63bf6030ce
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Introduce the gen-header command to the tool, enabling developers to
create language bindings. Currently, it supports generating C headers
from a transfer list.
Change-Id: Ibec75639c38577802d5abe55c7bc718740aad2b8
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Add tox to automate testing across multiple environments, ensuring code
robustness and compatibility with different Python versions. This helps
ensure consistency in test environments so both development and CI
systems run tests uniformly, and simplifies the execution of tasks like
linting and other commands with a single command.
Change-Id: I522adb486e89abecb9a130941ce4cef31332193a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
According to the specifications, the DLME launch should occur with
the cache disabled. Initially, the cache was enabled to enhance
performance. However, to comply with the PSCI specification, we
decided to disable it before launching the DLME.
Also, ensure that full DLME region is invalidated.
Change-Id: Idf619afb7e4a34ebe213bd3b559105ade993f3ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
This new version uses the multipart PSA AEAD API;
the authentication tag is verified via
a call to psa_aead_verify.
Change-Id: If4b7e6258223ae6fead1794d3e8d0004f0f387b3
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
MbedTLS 3.6.1 fixed the issue which previously
produced this warning, so this hack is no longer
necessary.
Change-Id: I934adefbf2fed16e16b9d98bc8674125b70b08fc
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
This new update to the LTS branch of MbedTLS provides minor
enhancements and bug fixes; including some security
fixes, and a fix to a compilation warning which
previously affected TF-A.
Full patch notes to this MbedTLS update can be found at
https://github.com/Mbed-TLS/mbedtls/releases/tag/mbedtls-3.6.1.
Change-Id: I1a68dfcb52a8361c1689cb6ef12d265a6462fda3
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
The support for runtime-model has never been implemented by any SPMC.
Hence, remove the corresponding field from binding document.
Also, fix the incorrect description of the `managed-exit-virq` property.
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I0a5ef3f08202a8c76edd9a6e1ac680ac3a38ca60
The rpi3 does not initialize the generic timer in BL1, which is now
required to use the delay timer in the dTPM driver. This change sets the
counter frequency register (CNTFRQ) with the rpi3's system counter
frequency value, as a prerequisite for timer initialization, and then
initializes the generic timer all during BL1 setup.
Change-Id: I4e2475b63ce4a97653202f94f506b5d3edc4c1a7
Signed-off-by: Abhi Singh <abhi.singh@arm.com>
The CPU crypto is not default on when power up, need to enable it by
software.
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifee2eab55d9c13cef5f15926fb80016845e2a66d
Memory reservation for tf-a does not happen in
runtime if memory reservation node pre-exists in DT.
Presence of reserved area is checked and user is
warned if it pre-exists.
Change-Id: I50e18be942777747e9074bb9d8e0305a29c28178
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>
