Merge changes from topic "nxp-drivers/add-get-parent-callback" into integration

* changes:
  feat(nxp-clk): refactor clock enablement
  feat(nxp-clk): add get_parent callback
  fix(nxp-clk): broken UART clock initalization

drivers/nxp/clk/s32cc/s32cc_clk_drv.c

@@ -14,7 +14,7 @@
 #include <s32cc-clk-modules.h>
 #include <s32cc-clk-utils.h>
 
-#define MAX_STACK_DEPTH		(15U)
+#define MAX_STACK_DEPTH		(40U)
 
 /* This is used for floating-point precision calculations. */
 #define FP_PRECISION		(100000000UL)
@@ -52,33 +52,23 @@ static struct s32cc_clk_drv *get_drv(void)
 	return &driver;
 }
 
-static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth);
+static int enable_module(struct s32cc_clk_obj *module,
+			 const struct s32cc_clk_drv *drv,
+			 unsigned int depth);
 
-static int enable_clk_module(const struct s32cc_clk_obj *module,
-			     const struct s32cc_clk_drv *drv,
-			     unsigned int *depth)
+static struct s32cc_clk_obj *get_clk_parent(const struct s32cc_clk_obj *module)
 {
 	const struct s32cc_clk *clk = s32cc_obj2clk(module);
-	int ret;
-
-	ret = update_stack_depth(depth);
-	if (ret != 0) {
-		return ret;
-	}
-
-	if (clk == NULL) {
-		return -EINVAL;
-	}
 
 	if (clk->module != NULL) {
-		return enable_module(clk->module, depth);
+		return clk->module;
 	}
 
 	if (clk->pclock != NULL) {
-		return enable_clk_module(&clk->pclock->desc, drv, depth);
+		return &clk->pclock->desc;
 	}
 
-	return -EINVAL;
+	return NULL;
 }
 
 static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv,
@@ -145,14 +135,14 @@ static void enable_fxosc(const struct s32cc_clk_drv *drv)
 	}
 }
 
-static int enable_osc(const struct s32cc_clk_obj *module,
+static int enable_osc(struct s32cc_clk_obj *module,
 		      const struct s32cc_clk_drv *drv,
-		      unsigned int *depth)
+		      unsigned int depth)
 {
 	const struct s32cc_osc *osc = s32cc_obj2osc(module);
 	int ret = 0;
 
-	ret = update_stack_depth(depth);
+	ret = update_stack_depth(&depth);
 	if (ret != 0) {
 		return ret;
 	}
@@ -175,6 +165,17 @@ static int enable_osc(const struct s32cc_clk_obj *module,
 	return ret;
 }
 
+static struct s32cc_clk_obj *get_pll_parent(const struct s32cc_clk_obj *module)
+{
+	const struct s32cc_pll *pll = s32cc_obj2pll(module);
+
+	if (pll->source == NULL) {
+		ERROR("Failed to identify PLL's parent\n");
+	}
+
+	return pll->source;
+}
+
 static int get_pll_mfi_mfn(unsigned long pll_vco, unsigned long ref_freq,
 			   uint32_t *mfi, uint32_t *mfn)
 
@@ -313,9 +314,9 @@ static int program_pll(const struct s32cc_pll *pll, uintptr_t pll_addr,
 	return ret;
 }
 
-static int enable_pll(const struct s32cc_clk_obj *module,
+static int enable_pll(struct s32cc_clk_obj *module,
 		      const struct s32cc_clk_drv *drv,
-		      unsigned int *depth)
+		      unsigned int depth)
 {
 	const struct s32cc_pll *pll = s32cc_obj2pll(module);
 	const struct s32cc_clkmux *mux;
@@ -324,7 +325,7 @@ static int enable_pll(const struct s32cc_clk_obj *module,
 	uint32_t sclk_id;
 	int ret;
 
-	ret = update_stack_depth(depth);
+	ret = update_stack_depth(&depth);
 	if (ret != 0) {
 		return ret;
 	}
@@ -403,9 +404,20 @@ static void config_pll_out_div(uintptr_t pll_addr, uint32_t div_index, uint32_t
 	enable_odiv(pll_addr, div_index);
 }
 
-static int enable_pll_div(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_pll_div_parent(const struct s32cc_clk_obj *module)
+{
+	const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
+
+	if (pdiv->parent == NULL) {
+		ERROR("Failed to identify PLL DIV's parent\n");
+	}
+
+	return pdiv->parent;
+}
+
+static int enable_pll_div(struct s32cc_clk_obj *module,
 			  const struct s32cc_clk_drv *drv,
-			  unsigned int *depth)
+			  unsigned int depth)
 {
 	const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
 	uintptr_t pll_addr = 0x0ULL;
@@ -413,7 +425,7 @@ static int enable_pll_div(const struct s32cc_clk_obj *module,
 	uint32_t dc;
 	int ret;
 
-	ret = update_stack_depth(depth);
+	ret = update_stack_depth(&depth);
 	if (ret != 0) {
 		return ret;
 	}
@@ -526,15 +538,34 @@ static int enable_cgm_mux(const struct s32cc_clkmux *mux,
 				  mux_hw_clk, false);
 }
 
-static int enable_mux(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_mux_parent(const struct s32cc_clk_obj *module)
+{
+	const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
+	struct s32cc_clk *clk;
+
+	if (mux == NULL) {
+		return NULL;
+	}
+
+	clk = s32cc_get_arch_clk(mux->source_id);
+	if (clk == NULL) {
+		ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n",
+		      mux->source_id, mux->index);
+		return NULL;
+	}
+
+	return &clk->desc;
+}
+
+static int enable_mux(struct s32cc_clk_obj *module,
 		      const struct s32cc_clk_drv *drv,
-		      unsigned int *depth)
+		      unsigned int depth)
 {
 	const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
 	const struct s32cc_clk *clk;
 	int ret = 0;
 
-	ret = update_stack_depth(depth);
+	ret = update_stack_depth(&depth);
 	if (ret != 0) {
 		return ret;
 	}
@@ -553,6 +584,7 @@ static int enable_mux(const struct s32cc_clk_obj *module,
 	switch (mux->module) {
 	/* PLL mux will be enabled by PLL setup */
 	case S32CC_ARM_PLL:
+	case S32CC_PERIPH_PLL:
 		break;
 	case S32CC_CGM1:
 		ret = enable_cgm_mux(mux, drv);
@@ -569,13 +601,24 @@ static int enable_mux(const struct s32cc_clk_obj *module,
 	return ret;
 }
 
-static int enable_dfs(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_dfs_parent(const struct s32cc_clk_obj *module)
+{
+	const struct s32cc_dfs *dfs = s32cc_obj2dfs(module);
+
+	if (dfs->parent == NULL) {
+		ERROR("Failed to identify DFS's parent\n");
+	}
+
+	return dfs->parent;
+}
+
+static int enable_dfs(struct s32cc_clk_obj *module,
 		      const struct s32cc_clk_drv *drv,
-		      unsigned int *depth)
+		      unsigned int depth)
 {
 	int ret = 0;
 
-	ret = update_stack_depth(depth);
+	ret = update_stack_depth(&depth);
 	if (ret != 0) {
 		return ret;
 	}
@@ -722,9 +765,21 @@ static int init_dfs_port(uintptr_t dfs_addr, uint32_t port,
 	return 0;
 }
 
-static int enable_dfs_div(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *
+get_dfs_div_parent(const struct s32cc_clk_obj *module)
+{
+	const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
+
+	if (dfs_div->parent == NULL) {
+		ERROR("Failed to identify DFS divider's parent\n");
+	}
+
+	return dfs_div->parent;
+}
+
+static int enable_dfs_div(struct s32cc_clk_obj *module,
 			  const struct s32cc_clk_drv *drv,
-			  unsigned int *depth)
+			  unsigned int depth)
 {
 	const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
 	const struct s32cc_pll *pll;
@@ -733,7 +788,7 @@ static int enable_dfs_div(const struct s32cc_clk_obj *module,
 	uint32_t mfi, mfn;
 	int ret = 0;
 
-	ret = update_stack_depth(depth);
+	ret = update_stack_depth(&depth);
 	if (ret != 0) {
 		return ret;
 	}
@@ -762,12 +817,69 @@ static int enable_dfs_div(const struct s32cc_clk_obj *module,
 	return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn);
 }
 
-static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth)
+typedef int (*enable_clk_t)(struct s32cc_clk_obj *module,
+			    const struct s32cc_clk_drv *drv,
+			    unsigned int depth);
+
+static int no_enable(struct s32cc_clk_obj *module,
+		     const struct s32cc_clk_drv *drv,
+		     unsigned int depth)
+{
+	return 0;
+}
+
+static int exec_cb_with_refcount(enable_clk_t en_cb, struct s32cc_clk_obj *mod,
+				 const struct s32cc_clk_drv *drv, bool leaf_node,
+				 unsigned int depth)
 {
-	const struct s32cc_clk_drv *drv = get_drv();
 	int ret = 0;
 
-	ret = update_stack_depth(depth);
+	if (mod == NULL) {
+		return 0;
+	}
+
+	ret = update_stack_depth(&depth);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/* Refcount will be updated as part of the recursivity */
+	if (leaf_node) {
+		return en_cb(mod, drv, depth);
+	}
+
+	if (mod->refcount == 0U) {
+		ret = en_cb(mod, drv, depth);
+	}
+
+	if (ret == 0) {
+		mod->refcount++;
+	}
+
+	return ret;
+}
+
+static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module);
+
+static int enable_module(struct s32cc_clk_obj *module,
+			 const struct s32cc_clk_drv *drv,
+			 unsigned int depth)
+{
+	struct s32cc_clk_obj *parent = get_module_parent(module);
+	static const enable_clk_t enable_clbs[8] = {
+		[s32cc_clk_t] = no_enable,
+		[s32cc_osc_t] = enable_osc,
+		[s32cc_pll_t] = enable_pll,
+		[s32cc_pll_out_div_t] = enable_pll_div,
+		[s32cc_clkmux_t] = enable_mux,
+		[s32cc_shared_clkmux_t] = enable_mux,
+		[s32cc_dfs_t] = enable_dfs,
+		[s32cc_dfs_div_t] = enable_dfs_div,
+	};
+	uint32_t index;
+	int ret = 0;
+
+	ret = update_stack_depth(&depth);
 	if (ret != 0) {
 		return ret;
 	}
@@ -776,53 +888,55 @@ static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth
 		return -EINVAL;
 	}
 
-	switch (module->type) {
-	case s32cc_osc_t:
-		ret = enable_osc(module, drv, depth);
-		break;
-	case s32cc_clk_t:
-		ret = enable_clk_module(module, drv, depth);
-		break;
-	case s32cc_pll_t:
-		ret = enable_pll(module, drv, depth);
-		break;
-	case s32cc_pll_out_div_t:
-		ret = enable_pll_div(module, drv, depth);
-		break;
-	case s32cc_clkmux_t:
-		ret = enable_mux(module, drv, depth);
-		break;
-	case s32cc_shared_clkmux_t:
-		ret = enable_mux(module, drv, depth);
-		break;
-	case s32cc_fixed_div_t:
-		ret = -ENOTSUP;
-		break;
-	case s32cc_dfs_t:
-		ret = enable_dfs(module, drv, depth);
-		break;
-	case s32cc_dfs_div_t:
-		ret = enable_dfs_div(module, drv, depth);
-		break;
-	default:
-		ret = -EINVAL;
-		break;
+	index = (uint32_t)module->type;
+
+	if (index >= ARRAY_SIZE(enable_clbs)) {
+		ERROR("Undefined module type: %d\n", module->type);
+		return -EINVAL;
+	}
+
+	if (enable_clbs[index] == NULL) {
+		ERROR("Undefined callback for the clock type: %d\n",
+		      module->type);
+		return -EINVAL;
+	}
+
+	parent = get_module_parent(module);
+
+	ret = exec_cb_with_refcount(enable_module, parent, drv,
+				    false, depth);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = exec_cb_with_refcount(enable_clbs[index], module, drv,
+				    true, depth);
+	if (ret != 0) {
+		return ret;
 	}
 
 	return ret;
 }
 
+static int enable_module_with_refcount(struct s32cc_clk_obj *module,
+				       const struct s32cc_clk_drv *drv,
+				       unsigned int depth)
+{
+	return exec_cb_with_refcount(enable_module, module, drv, false, depth);
+}
+
 static int s32cc_clk_enable(unsigned long id)
 {
+	const struct s32cc_clk_drv *drv = get_drv();
 	unsigned int depth = MAX_STACK_DEPTH;
-	const struct s32cc_clk *clk;
+	struct s32cc_clk *clk;
 
 	clk = s32cc_get_arch_clk(id);
 	if (clk == NULL) {
 		return -EINVAL;
 	}
 
-	return enable_module(&clk->desc, &depth);
+	return enable_module_with_refcount(&clk->desc, drv, depth);
 }
 
 static void s32cc_clk_disable(unsigned long id)
@@ -1115,9 +1229,79 @@ static int s32cc_clk_set_rate(unsigned long id, unsigned long rate,
 	return ret;
 }
 
+static struct s32cc_clk_obj *get_no_parent(const struct s32cc_clk_obj *module)
+{
+	return NULL;
+}
+
+typedef struct s32cc_clk_obj *(*get_parent_clb_t)(const struct s32cc_clk_obj *clk_obj);
+
+static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module)
+{
+	static const get_parent_clb_t parents_clbs[8] = {
+		[s32cc_clk_t] = get_clk_parent,
+		[s32cc_osc_t] = get_no_parent,
+		[s32cc_pll_t] = get_pll_parent,
+		[s32cc_pll_out_div_t] = get_pll_div_parent,
+		[s32cc_clkmux_t] = get_mux_parent,
+		[s32cc_shared_clkmux_t] = get_mux_parent,
+		[s32cc_dfs_t] = get_dfs_parent,
+		[s32cc_dfs_div_t] = get_dfs_div_parent,
+	};
+	uint32_t index;
+
+	if (module == NULL) {
+		return NULL;
+	}
+
+	index = (uint32_t)module->type;
+
+	if (index >= ARRAY_SIZE(parents_clbs)) {
+		ERROR("Undefined module type: %d\n", module->type);
+		return NULL;
+	}
+
+	if (parents_clbs[index] == NULL) {
+		ERROR("Undefined parent getter for type: %d\n", module->type);
+		return NULL;
+	}
+
+	return parents_clbs[index](module);
+}
+
 static int s32cc_clk_get_parent(unsigned long id)
 {
-	return -ENOTSUP;
+	struct s32cc_clk *parent_clk;
+	const struct s32cc_clk_obj *parent;
+	const struct s32cc_clk *clk;
+	unsigned long parent_id;
+	int ret;
+
+	clk = s32cc_get_arch_clk(id);
+	if (clk == NULL) {
+		return -EINVAL;
+	}
+
+	parent = get_module_parent(clk->module);
+	if (parent == NULL) {
+		return -EINVAL;
+	}
+
+	parent_clk = s32cc_obj2clk(parent);
+	if (parent_clk == NULL) {
+		return -EINVAL;
+	}
+
+	ret = s32cc_get_clk_id(parent_clk, &parent_id);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (parent_id > (unsigned long)INT_MAX) {
+		return -E2BIG;
+	}
+
+	return (int)parent_id;
 }
 
 static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id)

drivers/nxp/clk/s32cc/s32cc_clk_modules.c

@@ -192,12 +192,21 @@ static struct s32cc_clk_array s32cc_arch_clocks = {
 	.n_clks = ARRAY_SIZE(s32cc_arch_clk_list),
 };
 
+static const struct s32cc_clk_array *s32cc_clk_table[2] = {
+	&s32cc_hw_clocks,
+	&s32cc_arch_clocks,
+};
+
 struct s32cc_clk *s32cc_get_arch_clk(unsigned long id)
 {
-	static const struct s32cc_clk_array *clk_table[2] = {
-		&s32cc_hw_clocks,
-		&s32cc_arch_clocks,
-	};
-
-	return s32cc_get_clk_from_table(clk_table, ARRAY_SIZE(clk_table), id);
+	return s32cc_get_clk_from_table(s32cc_clk_table,
+					ARRAY_SIZE(s32cc_clk_table),
+					id);
+}
+
+int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id)
+{
+	return s32cc_get_id_from_table(s32cc_clk_table,
+				       ARRAY_SIZE(s32cc_clk_table),
+				       clk, id);
 }

drivers/nxp/clk/s32cc/s32cc_clk_utils.c

@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+#include <errno.h>
 #include <s32cc-clk-ids.h>
 #include <s32cc-clk-utils.h>
 
@@ -42,3 +43,23 @@ struct s32cc_clk *s32cc_get_clk_from_table(const struct s32cc_clk_array *const *
 
 	return NULL;
 }
+
+int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr,
+			    size_t size, const struct s32cc_clk *clk,
+			    unsigned long *clk_index)
+{
+	size_t i, j;
+
+	for (i = 0; i < size; i++) {
+		for (j = 0; j < clk_arr[i]->n_clks; j++) {
+			if (clk_arr[i]->clks[j] != clk) {
+				continue;
+			}
+
+			*clk_index = S32CC_CLK(clk_arr[i]->type_mask, j);
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}

drivers/nxp/clk/s32cc/s32cc_early_clks.c

@@ -17,7 +17,7 @@
 #define S32CC_PERIPH_PLL_VCO_FREQ	(2U * GHZ)
 #define S32CC_PERIPH_PLL_PHI3_FREQ	UART_CLOCK_HZ
 
-static int enable_fxosc_clk(void)
+static int setup_fxosc(void)
 {
 	int ret;
 
@@ -26,15 +26,10 @@ static int enable_fxosc_clk(void)
 		return ret;
 	}
 
-	ret = clk_enable(S32CC_CLK_FXOSC);
-	if (ret != 0) {
-		return ret;
-	}
-
 	return ret;
 }
 
-static int enable_arm_pll(void)
+static int setup_arm_pll(void)
 {
 	int ret;
 
@@ -53,20 +48,10 @@ static int enable_arm_pll(void)
 		return ret;
 	}
 
-	ret = clk_enable(S32CC_CLK_ARM_PLL_VCO);
-	if (ret != 0) {
-		return ret;
-	}
-
-	ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0);
-	if (ret != 0) {
-		return ret;
-	}
-
 	return ret;
 }
 
-static int enable_periph_pll(void)
+static int setup_periph_pll(void)
 {
 	int ret;
 
@@ -85,16 +70,6 @@ static int enable_periph_pll(void)
 		return ret;
 	}
 
-	ret = clk_enable(S32CC_CLK_PERIPH_PLL_VCO);
-	if (ret != 0) {
-		return ret;
-	}
-
-	ret = clk_enable(S32CC_CLK_PERIPH_PLL_PHI3);
-	if (ret != 0) {
-		return ret;
-	}
-
 	return ret;
 }
 
@@ -170,17 +145,12 @@ int s32cc_init_early_clks(void)
 
 	s32cc_clk_register_drv();
 
-	ret = enable_fxosc_clk();
+	ret = setup_fxosc();
 	if (ret != 0) {
 		return ret;
 	}
 
-	ret = enable_arm_pll();
-	if (ret != 0) {
-		return ret;
-	}
-
-	ret = enable_periph_pll();
+	ret = setup_arm_pll();
 	if (ret != 0) {
 		return ret;
 	}
@@ -195,6 +165,11 @@ int s32cc_init_early_clks(void)
 		return ret;
 	}
 
+	ret = setup_periph_pll();
+	if (ret != 0) {
+		return ret;
+	}
+
 	ret = enable_uart_clk();
 	if (ret != 0) {
 		return ret;

include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h

@@ -11,7 +11,12 @@ struct s32cc_clk *s32cc_get_clk_from_table(const struct s32cc_clk_array *const *
 					   size_t size,
 					   unsigned long clk_id);
 
+int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr,
+			    size_t size, const struct s32cc_clk *clk,
+			    unsigned long *clk_index);
+
 struct s32cc_clk *s32cc_get_arch_clk(unsigned long id);
+int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id);
 
 void s32cc_clk_register_drv(void);