Commit graph

16093 commits

Author SHA1 Message Date
Leo Yan
d1de6b2b57 feat(tc): enable stack protector
Enable the compiler's stack protector for detecting stack overflow
issues.

Though TC platform can generate RNG from RSE via MHU channel, the
stack protector canary is used prior to MHU channel initialization.

Thus, currently here simply returns a value of the combination of a
timer's value and a compile-time constant.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I68fcc7782637b2b6b4dbbc81bc15df8c5ce0040b
2025-01-31 13:45:28 +01:00
Olivier Deprez
cc7f37137e Merge "chore(deps): add LTS Dependabot configuration" into integration 2025-01-31 13:37:02 +01:00
Olivier Deprez
a2c5171461 Merge "fix(intel): update debug messages to appropriate class" into integration 2025-01-31 12:02:18 +01:00
Olivier Deprez
5cef096e4c Merge "fix(intel): update warm reset routine and bootscratch register usage" into integration 2025-01-31 12:01:35 +01:00
Olivier Deprez
de5943f94c Merge changes from topic "Id18b0341353ffc00e44e2d3c643ccdd05cc20c4f" into integration
* changes:
  fix(rk3399): fix unquoted .incbin for clang
  fix(rk3399): mark INCBIN-generated sections as SHF_ALLOC
2025-01-31 11:52:13 +01:00
Olivier Deprez
3ce41dc7cc Merge "fix(rdv3): add console name to checksum calculation on RD-V3" into integration 2025-01-31 10:36:12 +01:00
Manish V Badarkhe
ea370b041a Merge "docs(changelog): remove FEAT_XXXX scopes" into integration 2025-01-30 20:47:05 +01:00
Govindraj Raja
9b494c2d19 docs(changelog): remove FEAT_XXXX scopes
We have one entry per CPU features but most of the time we just add
CPU feature and its not touched again, so considering to generalize
anything with FEAT_XXXX additions to use `cpufeat` as subsection scope.

Also, some time we don't add a scope for CPU feature this causes problem
while generating release notes as CPU feature additions ends up in wrong
section.

Change-Id: Ibc80f6cdab9ae10ec3af1485640f46771b382da0
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2025-01-30 10:27:50 -06:00
Manish Pandey
a2ea98598c Merge "fix(versal-net): remove_redundant_lock_defs" into integration 2025-01-30 16:32:41 +01:00
Olivier Deprez
cf084b3620 Merge "fix(gicv3): do not assume redistributors are powered down" into integration 2025-01-30 16:27:44 +01:00
Govindraj Raja
ff82102505 Merge "feat(mediatek): add gic driver" into integration 2025-01-29 23:08:26 +01:00
Govindraj Raja
35c54de149 Merge "refactor(mediatek): refactor the data type of the return value" into integration 2025-01-29 22:57:15 +01:00
Manish V Badarkhe
206dd2bb3e Merge "fix(tc): fix compilation error" into integration 2025-01-29 22:09:56 +01:00
Manish Pandey
c2673bff18 Merge "fix(build): do not force PLAT in plat_helpers.mk" into integration 2025-01-29 13:58:46 +01:00
Yann Gautier
27f7083227 Merge "fix(xilinx): remove unused write_icc_asgi1r_el1()" into integration 2025-01-29 10:54:33 +01:00
Michal Simek
1c12cd10fc fix(xilinx): remove unused write_icc_asgi1r_el1()
The commit 427e46ddea ("fix(xilinx): fix sending sgi to linux")
removed code which called write_icc_asgi1r_el1() but function itself
wasn't removed.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I95a1424b0546f3f4a5e4611de34441b96e70b7d3
2025-01-29 10:52:59 +01:00
Leo Yan
26a520b2be fix(tc): fix compilation error
When the SPD_spmd configuration is disabled, the compiler complaints:

plat/arm/board/tc/tc_bl2_dpe.c:234:22: error: unused variable 'array_size' [-Werror=unused-variable]
  234 |         const size_t array_size = ARRAY_SIZE(tc_dpe_metadata);
      |                      ^~~~~~~~~~
plat/arm/board/tc/tc_bl2_dpe.c:233:16: error: unused variable 'i' [-Werror=unused-variable]
  233 |         size_t i;
      |                ^
cc1: all warnings being treated as errors

Move variable declarations into the code chunk protected by the SPD_spmd
configuration.

Change-Id: I1a3889938e2d4ec5efec516e9ef54034f9d711b2
Signed-off-by: Leo Yan <leo.yan@arm.com>
2025-01-29 09:49:18 +00:00
Madhukar Pappireddy
604b879778 Merge "fix(el3-spmc): move ERROR line inside conditional" into integration 2025-01-29 00:52:43 +01:00
Madhukar Pappireddy
eb2215d2e7 Merge "feat(el3-spmc): use spmd_smc_switch_state after secure interrupt" into integration 2025-01-29 00:46:06 +01:00
Govindraj Raja
2c09bf93f0 Merge changes I3f63d597,I40fc21f5 into integration
* changes:
  feat(mt8196): add mtcmos driver
  feat(mt8196): add DCM driver
2025-01-28 22:08:16 +01:00
Govindraj Raja
cf2df874cd Merge changes I1126311e,I6ae5b5b4,I1b907256,I9facb6bf,Ie51cffeb, ... into integration
* changes:
  feat(mt8196): add vcore dvfs drivers
  feat(mt8196): add LPM v2 support
  feat(mt8196): add SPM common version support
  feat(mt8196): add SPM common driver support
  feat(mt8196): add SPM basic features support
  feat(mt8196): add SPM features support
  feat(mt8196): enable PMIC low power setting
  feat(mt8196): add mcdi driver
  feat(mt8196): add pwr_ctrl module for CPU power management
  feat(mt8196): add mcusys moudles for power management
  feat(mt8196): add CPC module for power management
  feat(mt8196): add topology module for power management
  feat(mt8196): add SPMI driver
  feat(mt8196): add PMIC driver
2025-01-28 22:07:51 +01:00
Guangjie Song
1f913a6e3a feat(mt8196): add mtcmos driver
add mtcmos driver for ufs power control

Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I3f63d5976906aaca91a71a147497e9345339774d
2025-01-28 21:59:52 +01:00
Guangjie Song
e578702f71 feat(mt8196): add DCM driver
DCM means dynamic clock management, and it can dynamically slow down
or gate clocks during CPU or bus idle.

Add MCUSYS or bus related DCM drivers.
Enable MCUSYS or bus related DCM by default.

Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I40fc21f5808962ca46870a2f3b9963dc8088f877
2025-01-28 21:59:03 +01:00
Manish V Badarkhe
fc45c16b46 Merge "fix(rdv3): fix comment for DRAM1 carveout size" into integration 2025-01-28 18:11:12 +01:00
Manish V Badarkhe
c2f05915bd Merge changes from topic "upstream_sp_num" into integration
* changes:
  fix(tc): enable certificate on the last secure partition
  feat(sptool): populate secure partition number in makefile
2025-01-28 18:01:23 +01:00
Manish V Badarkhe
64187603b2 Merge "fix(stm32mp2): correct early/crash console init" into integration 2025-01-28 15:28:25 +01:00
Ben Horgan
2e361319ac fix(tc): enable certificate on the last secure partition
Distros (e.g. Buildroot and Android) can have different secure partition
layout.

This commit iterates the DPE metadata table and finds index (i) for the
first entry of the secure partition, connecting with the defined secure
partition number NUM_SP, so the last secure partition index is:

   i + NUM_SP - 1

Instead of setting the certificate in hard code, dynamically enables the
certificate for the last secure partition base on calculated index.

Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: Idd11b4f463bf5ccc8d82cd06bd21deeebbda67d9
2025-01-28 14:08:18 +00:00
Boerge Struempfel
23647bd52c
fix(stm32mp2): correct early/crash console init
The previous code used 64-bit registers as the target and source for
load and store operations on 32-bit hardware registers. In certain
cases (e.g., when using USART1 as the debug console), this could result
in deadlocks where the A35 gets stuck in a permanent loop due to test
conditions that are never fulfilled.

To resolve this issue, 32-bit registers are now used for these
operations.

Change-Id: Id2c03a1df26738fe815079da042cc2dd989f4f8e
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>
2025-01-28 15:04:32 +01:00
Chris Kay
522c175d2d chore(deps): add LTS Dependabot configuration
This is an experimental change which (hopefully) enables Dependabot on
the LTS branches, and ensures that PRs touching the package management
files in the repository assign the proper developer(s) as reviewers.

Change-Id: Iefa2f46325514026969fabd08e550544dcb4a598
Signed-off-by: Chris Kay <chris.kay@arm.com>
2025-01-28 14:03:56 +00:00
Rakshit Goyal
4e2369c707 fix(rdv3): fix comment for DRAM1 carveout size
Corrected the comment for the size of NRD_CSS_DRAM1_CARVEOUT_SIZE
(0x0C000000) from 117MB to 192MB

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I289d37f50e70b936f717d4579d73882fac28ee95
2025-01-28 13:56:33 +00:00
Olivier Deprez
4c23d62746 Merge "fix(spmd): fix build failure due to redefinition" into integration 2025-01-28 08:23:13 +01:00
Manish Pandey
b53089d8b2 Merge "feat(pmuv3): setup per world MDCR_EL3" into integration 2025-01-27 19:11:37 +01:00
Madhukar Pappireddy
70a7fc8a22 Merge changes I95bb84b0,I2dfa62ac,I4017e44b into integration
* changes:
  feat(stm32mp2-fdts): add STM32MP257F-DK board support
  fix(stm32mp2-fdts): fix SDMMC slew rate
  feat(stm32mp2-fdts): add LPDDR4 files
2025-01-27 16:49:50 +01:00
Ben Horgan
93273613b4 feat(sptool): populate secure partition number in makefile
Calculate the secure partition number and saves it into the defined
macro NUM_SP.

Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: I4175a10d315482b65fd0f3eed4c6fd1e1e2b5e4d
2025-01-26 17:40:03 +00:00
Lauren Wehrmeister
bba792b165 Merge changes Ided750de,Id3cc887c into integration
* changes:
  docs(gxl): add build instructions for booting BL31 from U-Boot SPL
  feat(gxl): add support for booting from U-Boot SPL/with standard params
2025-01-24 23:26:44 +01:00
Bipin Ravi
8d468e586e Merge "docs(maintainers): update LTS maintainers" into integration 2025-01-24 21:48:48 +01:00
Govindraj Raja
52e5a3f1e2 docs(maintainers): update LTS maintainers
Updating LTS maintainers list as agreed with other LTS
maintainers.

Change-Id: Ibf087c6b0e24d6faa9dafb6f8a0955a47f583f28
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2025-01-24 11:25:51 -06:00
Mateusz Sulimowicz
c95aa2eb0d feat(pmuv3): setup per world MDCR_EL3
MDCR_EL3 register will context switch across all worlds. Thus the pmuv3
init has to be part of context management initialization.

Change-Id: I10ef7a3071c0fc5c11a93d3c9c2a95ec8c6493bf
Signed-off-by: Mateusz Sulimowicz <matsul@google.com>
2025-01-24 10:09:08 +00:00
Manish V Badarkhe
d9f9ad0b09 Merge changes I10a3fc1d,I3aed6228 into integration
* changes:
  fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu
  fix(tc): fix SMMU streamId for tc4 gpu
2025-01-24 09:59:23 +01:00
Yann Gautier
fffde230ba Merge changes from topic "xlnx_fix_plat_single_ret" into integration
* changes:
  fix(versal2): modify function to have single return
  fix(versal-net): modify function to have single return
  fix(versal): modify function to have single return
  fix(xilinx): modify function to have single return
  fix(zynqmp): modify function to have single return
  fix(versal-net): add unsigned suffix to match data type
  fix(versal): add unsigned suffix to match data type
  fix(versal2): add missing curly braces
  fix(versal-net): add missing curly braces
  fix(zynqmp): add missing curly braces
2025-01-23 11:22:47 +01:00
Yann Gautier
5e36111422 Merge "fix(xilinx): dcc console tests failing" into integration 2025-01-23 11:19:54 +01:00
Manish V Badarkhe
bf6b151390 Merge changes I70b68b06,I7b180c3e,Id4ad925d,Ie31933e0,Ie8fe1f1d, ... into integration
* changes:
  refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM
  fix(tc): modify ethernet configuration for TC4 FPGA
  fix(tc): modify gpio controller base addr for TC4 FPGA
  fix(tc): modify DPU configuration in dts for TC4 FPGA
  fix(tc): modify mmc configuration for TC4 FPGA
  feat(tc): configure UART for TC4 FPGA
2025-01-23 10:41:35 +01:00
Bipin Ravi
d838205951 Merge changes from topic "gr/lts-doc" into integration
* changes:
  docs: updates to LTS
  docs: add inital lts doc
2025-01-22 18:16:53 +01:00
Kunlong Wang
f0dce79600 feat(mt8196): add vcore dvfs drivers
- VCORE DVFS is the feature to change VCORE/DDR Freq for power saving
- When there are no requests for using Vcore/DRAM, Vcore DVFS will
- lower the voltage and frequency of Vcore/DRAM to achieve power saving.

Signed-off-by: Kunlong Wang <kunlong.wang@mediatek.com>
Change-Id: I1126311e8b3943cc54fb13e15973b9e1b74c129e
2025-01-22 15:28:08 +08:00
Wenzhen Yu
da8cc41bc8 feat(mt8196): add LPM v2 support
LPM means low power module, it will connect idle and SPM to achieve
lower power consumption in some scenarios, and this patch is LPM
second version

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.corp-partner.google.com>
Change-Id: I6ae5b5b4c2056d08c29efab5116be3a92351d8f1
2025-01-22 15:28:08 +08:00
Wenzhen Yu
5532feb70c feat(mt8196): add SPM common version support
This patch provides common APIs for communication with other subsystems
as well as common APIs for collecting the clock and power status of
each subsystem.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I1b907256f53578a58d74d66beec7140edf41f687
2025-01-22 15:28:08 +08:00
Wenzhen Yu
a24b53e0e5 feat(mt8196): add SPM common driver support
This patch mainly initializes the SPM and provides common APIs for SPM
to enable the use of its various features.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I9facb6bf9962bb2d5fcacd945846bfaeb4c87a55
2025-01-22 15:28:08 +08:00
Wenzhen Yu
fb57af70ae feat(mt8196): add SPM basic features support
This patch mainly collects and organizes SPM state information to
facilitate debugging when issues arise.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: Ie51cffeb1d683d65d88701fc63c426b20b22492f
2025-01-22 15:28:08 +08:00
Wenzhen Yu
01ce1d5d2f feat(mt8196): add SPM features support
When the system is in idle or suspend state, SPM will turn off some
unused system resources. This patch enables this feature to achieve
power saving.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: Ia9764b91073c4765d41fe7fcd8e4a21372c290f1
2025-01-22 15:28:08 +08:00
Wenzhen Yu
e8e87683f2 feat(mt8196): enable PMIC low power setting
During suspend, it is necessary to set some power rails of the PMIC
to enter low power mode to achieve power saving.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: Iaeadd15270e0209f027fab80f478ad621bd59ea7
2025-01-22 15:27:52 +08:00