There are no existing users of pm_ioctl_set_sgmii_mode() API so
cleanup the dead code.
Change-Id: I1088d2f5c944bf54fc5fdd554360bdd321ad798a
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal NET platform. TSP is a component for testing and validating
secure OS and trusted execution environments.
If a BL32 image is present, then there must be a matching Secure-EL1
Payload Dispatcher (SPD) service called TSPD, this service is
responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of BL32
once the runtime services are fully initialized. BL31 invokes such
a registered function to initialize BL32 before running BL33.
The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3 This is
because the S-EL1 can use GIC system registers to manage interrupts
and does not need GIC interface base addresses to be configured.
The secure code load address is initially being pointed to 0x0 in the
handoff parameters, which is different from the default or user-provided
load address of 0x60000000. In this case, set up the PC to the
requested BL32_BASE address to ensure that the secure code is loaded
and executed from the correct location.
Change-Id: I58fe256dc9d6be5cee384c5ebb9baca2737c02a6
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal platform. TSP is a component for testing and validating
secure OS and trusted execution environments.
If a BL32 image is present, then there must be a matching Secure-
EL1 Payload Dispatcher (SPD) service called TSPD, this service
is responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of
BL32 once the runtime services are fully initialized. BL31 invokes
such a registered function to initialize BL32 before running BL33.
The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3
This is because the S-EL1 can use GIC system registers to manage
interrupts and does not need GIC interface base addresses to be
configured.
The secure code load address is initially being pointed to 0x0
in the handoff parameters, which is different from the default
or user-provided load address of 0x60000000. In this case, set up
the PC to the requested BL32_BASE address to ensure that the secure
code is loaded and executed from the correct location.
Change-Id: Ida0fc6467a10bfde8927ff9b3755a83f3e16f068
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Updated the generic TSP makefile in the common path for reuse in
different platforms.
Change-Id: Idd14675bc547e0a4a95132653a181e7ff39a547a
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Reorganized TSP code into common folder, updated paths in
tsp-zynqmp.mk. Handling the return value of a console registration
function.
Change-Id: I848f17c3417b3e8c8cbd2058e9642ed13d121325
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Refactor two platform specific functions, plat_versal_get_mmap() and
plat_versal_net_get_mmap(), to use a more generic function name
plat_get_mmap(). The function can be used in the common code to
obtain memory region.
Change-Id: I3eeb24aff217eef30af60a7742cbebe9d3b2edce
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Retain assertions in builds for TF-A run from DDR with
ENABLE_ASSERTIONS=1. It helps to catch programming errors
(e.g. bad argument provided by platform porting function)
code size change is 4k.
For debug builds, assertions are enabled by default.
The same change is done by Tegra: plat/nvidia/tegra/platform.mk.
Change-Id: I1790862616faddf68b4d533750722dad27cae269
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Retain assertions in release builds by building TF-A with
ENABLE_ASSERTIONS=1. It helps to catch programming errors
(e.g. bad argument provided by platform porting function)
in release builds as well.
code size change is 4k.
For debug builds, assertions are enabled by default.
The same change is done by Tegra: plat/nvidia/tegra/platform.mk
Change-Id: I0db4b82d42d115866a3ed43933edbfc46ac7406a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Retain assertions in release builds by building TF-A with
ENABLE_ASSERTIONS=1. It helps to catch programming errors
(e.g. bad argument provided by platform porting function)
in release builds as well.
code size change is 4k.
For debug builds, assertions are enabled by default.
The same change is done by Tegra: plat/nvidia/tegra/platform.mk.
Change-Id: Ie801fa9a326596ebef71be870b95a3cf9077ad20
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Typecast the base and size arguments for build time as unsigned
integers and the limit derived from these two as an unsigned long
to prevent size integer overflow issues during the build.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Iefc148e0091e8c8a4ca505691036c79528a558a4
Switch boot console to runtime at bl31_plat_runtime_setup() for all Xilinx
SOCs to follow default behavior. Till now boot console is used for the
whole lifecycle of TF-A. On the other hand there is no option to configure
different boot and run time console that's why this isn't really a issue.
Documentation is describing default behavior like this:
"
Function : bl31_plat_runtime_setup() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : void
Return : void
The purpose of this function is allow the platform to perform any BL31 runtime
setup just prior to BL31 exit during cold boot. The default weak
implementation of this function will invoke ``console_switch_state()`` to switch
console output to consoles marked for use in the ``runtime`` state.
"
Change-Id: I08baa722dfd8b37b4440e84accf3baaeb01a686f
Signed-off-by: Michal Simek <michal.simek@amd.com>
Introduces functionality to retrieve console information from the
device tree (DTB) and use it in TF-A code.
Comparing early console information and the data populated from
the DTB. In case of a mistmatch, the changes takes care of
unregistering the build time console configuration and registering the
DTB-based console.
Reorganizes the console configuration setup in BL31 by moving it to a
dedicated function called setup_console() in the plat_console.c
file. This change improves code readability by isolating console-
related settings, making it easier to manage and extend the console
configuration in the future.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I7b6ebad0e91133ab5fbda8f3a8663abfb6dd2458
Introduces functionality to retrieve console information from the
device tree (DTB) and use it in TF-A code.
Comparing early console information and the data populated from
the DTB. In case of a mistmatch, the changes takes care of
unregistering the build time console configuration and registering the
DTB-based console.
Reorganizes the console configuration setup in BL31 by moving it to a
dedicated function called setup_console() in the plat_console.c
file. This change improves code readability by isolating console-related
settings, making it easier to manage and extend the console
configuration in the future.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I617c846d753e73d2433edf15b3286f1a650f01b3
Refactors the code in the AMD-Xilinx platform for Versal and Versal NET
to create a more generic function for obtaining clock signals
from the platform. The new function get_uart_clk is specific to each
platform and providing greater flexibility for clock signal retrieval
in various parts of the codebase.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Iff67315339b2651c9bea73af0d89fcbad2bb332a
Introduces functionality to retrieve console information from the
device tree (DTB) and use it in TF-A code.
With fdt_get_stdout_node_offset() function, which reads the 'secure-chosen'
first,'chosen' and 'stdout-path' properties from the DTB, providing a
convenient and standardized way to access serial console information.
Implemented a comparison mechanism between early console information
and the data populated from the DTB. In case of a mismatch, the commit
takes care of unregistering the build-time console configuration and
registering the DTB-based console.
Reorganizes the console configuration setup in BL31 by moving it to a
dedicated function called setup_console() in the plat_console.c
file. This change improves code readability by isolating
console-related settings, making it easier to manage and extend the
console configuration in the future.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I857042fc0fb8f070bbc11f6b47aa57a72fbe5392
use common code definition and remove zynqmp local definition
for prepare_dtb in dtb flows.
Change-Id: I362b90b96852e9afccc8a2e23d3b7f709280fba7
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
presence of multiple return path in prepare_dtb results in misra c
violation 15.5: this return statement is not the final statement
in the compound statement that forms the body of the function.
prepare_dtb is refactored to address the same.
Change-Id: I17ca4314202d6ca8d6fb0c4ea2ed9d31a152371b
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Address an issue where incorrect macro name is being used for
setting the UART buad rate. Updated the code to use the
appropriate macro name, ensuring that baud rate name is proper.
Fixes: 04a483359f ("feat(xilinx): sync macro names")
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I27dd8b1559beb0cf7b872de037adc95a948ecc2f
If console is not found there is no way where to print information about
it. Currently only cdns/dcc/pl011 uarts are supported that's why remove
the message which none can see anyway.
But keep "else" part with comment to avoid misra c rule 15.7 violation
which is also missing in Versal NET implementation.
Change-Id: I78e3baffd2288d2a4673099bf193f22029912840
Signed-off-by: Michal Simek <michal.simek@amd.com>
There is no reason to have platform specific macros where generic
macros can be used. This is pretty much preparation step for moving
console code to single location where multiple combinations can be
easier to handle.
Change-Id: I4d85ddef29f5870a9ea9590d4d1564469c6eb87e
Signed-off-by: Michal Simek <michal.simek@amd.com>
CONSOLE_FLAG_CRASH should be also setup to get crash logs on
the same console. Both platforms are using crash console
implementation from plat/common/aarch64/crash_console_helpers.S
that's why there is necessary to setup CONSOLE_FLAG_CRASH.
plat_crash_console_putc() implementation is saying:
"int plat_crash_console_putc(char c)
Prints the character on all consoles registered with the console
framework that have CONSOLE_FLAG_CRASH set. Note that this is only
helpful for crashes that occur after the platform intialization code
has registered a console. Platforms using this implementation need to
ensure that all console drivers they use that have the CRASH flag set
support this (i.e. are written in assembly and comply to the register
clobber requirements of plat_crash_console_putc()."
Change-Id: I314cacbcb0bfcc85fe734882e38718f2763cdbf4
Signed-off-by: Michal Simek <michal.simek@amd.com>
Private plat_crash_console_init() has all the setup commented
that's why it was never been tested.
pl011 uart is supposed to be used as crash console and it should be
enought to add CONSOLE_FLAG_CRASH and remove platform specific
implementation and use generic one.
Early console can't be used for early ASM debugging but that's
expected and not required.
Change-Id: I1267fd78c0d6532a0baddbcad8a5b2a7dfc7750b
Signed-off-by: Michal Simek <michal.simek@amd.com>
flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related entry in the dcache.
Change-Id: Ide0ed58f799b35b690ed790c7498ecdc334e02f5
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I411deff57ab141fc2978a2e916aec2d988cb8f9c
The commit f123b91fdd ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a
("fix(versal-net): fix BLXX memory limits for user defined
values") fixed issue regarding linker alignment section.
But removing -1 logic is not reflected in plat_fdt() memory
reservation code.
That's why remove +1 from prepare_dtb() not to generate a reserved
memory node with bigger size which ends up with reserving more
space than actually requested by a full featured bootloader or OS.
Change-Id: I0a646cee7d5a55157a6eb1b672c2edbe89e6a57f
Signed-off-by: Michal Simek <michal.simek@amd.com>
Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will simply return.
Empty definition of prepare_dtb is removed.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Ie8a3ec51d60a7389831cfe6a112f722777930623
In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning is as mentioned in
Refer section 4.2.3 in
https://gcc.gnu.org/onlinedocs/gcc-3.0.2/cpp_4.html
Due to this,functionality for reservation of TF-A DDR memory in
dtb is never executed.
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Iafb6b7c6aec29bba22f8f7a8395f9caf97548157
All pending interrupts should be handled by their interrupt handlers. CPU
cores remain in suspend state if pending interrupts are cleared.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Change-Id: Id8ddf36cbcc07484f232c477277c4da106985c8f
The input argument clock_id in pm_api_clock_get_name function is not
validated against the maximum allowed number. This can lead to OOB
access for ext_clocks variable.
Add check in the pm_api_clock_get_name() to validate clock_id against
CLK_MAX.
Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: Ifa0033d2c557efd6a87b40e366560bc3ba8c602b
Make PMC IPI channel for Versal NET as secure so that NS
systems cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I75ba8796859dcb35644f3e144d7dc5926755ef78
Make PMC IPI channel for Versal as secure so that NS systems
cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I22148653fa2d27941cb3031ac790892cee0d1796
Add redundant macro call to increase security by making
code glitch immune as security operations might be
called with the IPI command.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I84d84cca258b7cd981f62816c51032341e19095c
Currently security flag is set to SECURE by default and
is changed to NON_SECURE if NS system is detected. In this
case NS system may access secure system if condition check
gets skipped due to glitches.
So, initialize security_flag to NON_SECURE_FLAG and switch
to SECURE_FLAG if the TrustZone bit is detected to be
in more secure state.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I7af54465bd8744ba97a58c02607631ee23619d47
Add common/debug.h and libfdt.h files to the common file
for XILINX_OF_BOARD_DTB_ADDR configuration.
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I577cc018eda34e186e48594a62c54eb55f11bbd3
As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE
APIs are not supported for the runtime operations in the firmware and
the TF-A it is already returning an error when there is any request
to access these APIs. So, just removing the unused code to avoid the
confusion around these APIs.
Also, there is no issue with the backward compatibility as these APIs
were never used since implemented. Hence no need to bump up the
version of the feature check API as well.
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Change-Id: I444f973e62cd25aae2e7f697d808210b265106ad
In ZynqMP, the function zynqmp_config_setup() is common between bl31
and bl32(TSP). This function initializes IPI configuration and
prints the chip idcode and revision on the console, which is already
done in bl31 and redundant in bl32(TSP).
Remove the legacy code, reading the chip idcode and
revision information through direct register read.
Change-Id: I5da8e75a597ac9c4e1b56346e065d29e2be8787f
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
TSP(bl32) requires secure interrupts to be handled at S-EL1.
Enable the ZynqMP to handle secure interrupts in S-EL1 by setting
GICV2_G0_FOR_EL3 to 0 in case of SPD=tspd build option.
For ZYNQMP_WDT_RESTART build option GICV2_G0_FOR_EL3 needs to be
enabled and thus for ZynqMP GICV2_G0_FOR_EL3 is set to 1 by default.
On GICv2, when GICV2_G0_FOR_EL3 is set to 1, Group 0 interrupts
target EL3. This allows GICv2 platforms to enable features requiring
EL3 interrupt type.
This also means that all GICv2 Group 0 interrupts are delivered
to EL3, and the Secure Payload interrupts needs to be synchronously
handed over to Secure EL1 for handling.
Change-Id: I7eb72c6588ab41730a74ece261050840646de037
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
In tf-a-ci-scripts repo, change commit 8ffa3d571b(ci(static-checks):
correct include order for *.S macro headers) provides a fix related
to header file include order in assembly files. With the above fix,
improper header order in assembly files has been detected.
Reorder the header includes in assembly files as per the update
in tf-a-ci-scripts.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I4a4f3c5bb73886dae234160b893470443f1424fc
In commit b9d26cd3c4 ("chore(xilinx): replace fsbl with xbl"),
function and variable names were changed, but the corresponding
function name in the functional documentation comments is not updated.
Update the function and variable names as per the above commit.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I7b777c21fe3673d29f809bf923eba38749f2c024
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
