Currently, the peripheral node indexes are incorrect
for Versal NET due to which incorrect node error is
generated and permission to set the device as wakeup
source is failed. Correct Versal NET peripheral node
indexes to fix above issue.
Fixes: 662aafd6475e ("feat(xilinx): add device node indexes")
Change-Id: I4a2d76f375645e13512599a0272d9322ff6fafd3
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Update the Warning message to be more informative
about the warning being printed.
Change-Id: I923dc5dd760908844d5e1ac8542fd1b04c9f0af5
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Versal NET platform supports multiple cpu clusters and the cluster
information for every partition contaning firmware component
is being passed by PLM through handoff parameters to TF-A.
Function implementation for getting cluster value for the firmware
component partition in TF-A and check for the firmware component
being targeted to be executed on Cluster 0.
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I8622699e12b0a9cda83ae46e2ad0a038ca377fda
Use the IPI command GET_HANDOFF_PARAM to get the PLM to TF-A handoff
parameters. The BL32/BL33 information from the handoff parameters will
be used by TF-A.
If no valid PLM to TF-A handoff parameters are available then,
the TF-A will fall back to the build time information or defaults
set in the TF-A for BL32/BL33.
Once the bootmode identification is supported the default configuration
will be done only for JTAG and for all other bootmodes PLM to TF-A
handoff parameters will be used.
Change-Id: Ia2204fe30fea6f32b4e5d2610820217e6ed23e4d
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
The handoff functionality is common between platforms and all
platforms do not use fsbl terminology. Renaming handoff related code
to generic naming.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ic250af927f33c4fecbc2e6bab01b83a6dd2aab52
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rearranged to ensure a consistent and
organized structure in the codebase, facilitating better
readability and maintainability.
https: //trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#headers-and-inclusion
https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/static-checks/
For example, to run header check:
/tf-a-ci-scripts/script/static-checks/check-include-order.py --tree ${PWD} > Includefileorder.txt
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ia5802722e69859596b94f31ec40755adbf7d865b
For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for the functional
documentation to make sure AMD-xilinx documentation is align with
actual code.
For example use kernel-doc from linux to call:
<linux>/scripts/kernel-doc -man -v 1 >/dev/null file...
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Idcc9def408b6c8da35b36f67ef82fc00890e998c
Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflow issue during build.
For zynqmp platform, calculating the limit without typecasting results
in build error as follows
make -j DEBUG=0 RESET_TO_BL31=1 PLAT=zynqmp \
ZYNQMP_ATF_MEM_BASE=0x70000000 ZYNQMP_ATF_MEM_SIZE=0x10000000 \
XILINX_OF_BOARD_DTB_ADDR=0x100000 bl31
plat/xilinx/zynqmp/include/platform_def.h:51:62:
error: integer overflow in expression of type 'int' results
in '-2147483648' [-Werror=overflow]
51 | # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE)
Change-Id: Id093a50e748884d4fba65626e94f361f6c23cecc
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
The commit 0ec6c31320 provides irq to device index mapping
which is required to check for IRQs and set peripheral as a
wake source if IRQ is enabled. But in that commit some IRQ
numbers are missed. Because of that, wakeup using some
peripheral interrupts will not work. Add those missing IRQ
numbers.
Fixes: 0ec6c31320 ("feat(versal): replace irq array with switch case")
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Icbc773050c328be253702e63e7cf8450c7dee133
The commit 8ce2fbffe3 ("fix(zynqmp): fix BLXX memory limits for user
defined values") fixed logic around BL31_LIMIT but didn't update
prepare_dtb() which is also using +1 logic.
Change-Id: Ia6de10d992a552ca9cfa39c14261b0f94cda95ec
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Don't use BL31_LIMIT macro for validation logic directly but clearly
mark BL31_LIMIT as 64bit address to avoid compilation error when
-Werror=logical-op is passed.
Likely caused by ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE is in 64bit
logic 0x100000000 and compiler handles it as 32bit value. That's why
error is shown.
Use uint64_t variable for limit and also for base.
Here is command line to replicate this issue:
make realclean; make -j PLAT=zynqmp DEBUG=1 RESET_TO_BL31=1 \
SPD=tspd SDEI_SUPPORT=1 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 \
ZYNQMP_ATF_MEM_SIZE=0x00040000 all -Werror=logical-op
Also error which is coming:
plat/xilinx/zynqmp/zynqmp_sdei.c: In function
'arm_validate_ns_entrypoint':
plat/xilinx/zynqmp/zynqmp_sdei.c:19:40: error: logical 'or' of
collectively exhaustive tests is always true [-Werror=logical-op]
19 | return (entrypoint < BL31_BASE ||
entrypoint > BL31_LIMIT) ? 0 : -1;
Change-Id: Ie1f1b4d2cd94b977aebb72786ecace0b062da418
Signed-off-by: Michal Simek <michal.simek@amd.com>
Since the Arm Trusted Firmware(ATF) has been renamed to Trusted
Firmware-A (TF-A), replace all the instances of ATF from code comments,
macros, variables and functions to TF-A.
Change-Id: Iab448d96158612a3effb4e49943f8d6cb43aaad5
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net): move macros to common header
feat(xilinx): add support to get chipid
Pack the structure and make id/ver smaller and sorted.
The change saves 400bytes in RODATA section.
Change-Id: I8bcbe8fd589ba193551a0dd2cd19572516252e73
Signed-off-by: Michal Simek <michal.simek@amd.com>
* changes:
feat(xilinx): fix IPI calculation for Versal/NET
feat(xilinx): setup local/remote id in header
feat(xilinx): clean macro names
fix(zynqmp): do not export apu_ipi
fix(zynqmp): remove unused headers
feat(xilinx): move IPI related macros to plat_ipi.h
Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal NET platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.
Change-Id: I6648051c7f5fa27d2f02080209da36ee8d5a9d95
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.
Change-Id: I1466a9ad1bc8dde1cda516ddd3edbaa6a5941237
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.
Change-Id: I355b024f5e870c6fc104598bc571dbaa29503ae2
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Add support for PM API SYS to get the chip ID from the target.
The API calls the IPI command to read the Chip idcode and revision.
Change-Id: Id4d7d812cbf77c5e2fc7785b8afb379214f8dd19
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker
file aligns section on a page boundary. So having the -1 in
the size calculations leads to an error message looking like this:
bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte
While at it fix all other occurences of predefined values that were
calculated with -1.
Fixes: 1d333e6909 ("feat(versal-net): add support for Xilinx
Versal NET platform")
Change-Id: I4455f63ee3ad52369f517a7d8d3627faf0b28c0f
Signed-off-by: Michal Simek <michal.simek@amd.com>
When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
aligns section on a page boundary. So having the -1 in the size
calculations leads to an error message looking like this:
bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte
While at it fix all other occurences of predefined values that were
calculated with -1
Fixes: commit f91c3cb1df ("arm64: versal: Add support for new Xilinx Versal ACAPs")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ica1f97867b701e7fcd60ea8ea07d2ae96c485443
When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
aligns section on a page boundary. So having the -1 in the size
calculations leads to an error message looking like this:
bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte
Commit 9b4ed0af02 ("feat(plat/zynqmp): fix section `coherent_ram' will not fit in region `RAM'")
applied a similar fix, but only in the predefined for BL31LIMIT/BASE.
While at it fix all other occurences of predefined values that were
calculated with -1
Fixes: 01555332fa ("zynqmp: Revise memory configuration options")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ic96e36808d01f6bb92e6839cec92fc52320dd3f3
The array type_el3_interrupt_table is defined for MAX_INTR_EL3(128)
elements and only two interrupts - ARM_IRQ_SEC_SGI_7(15), IRQ_TTC3_1(77)
are being handled. Current implementation is consuming 1024 bytes which
can be optimized for the number of interrupts to be handled.
The current array is replaced with the array of struct
zynmp_intr_info_type_el3_t (id and handler as member) and with
maximum number of interrupts to be handled as the size of array
(MAX_INTR_EL3 = 2). User is expected to adjust MAX_INTR_EL3 based on
how many interrupts are handled in TF-A.
With the updated implementation, a reduction of 960 bytes is observed.
Versal and Versal NET are using similar implementation introduced by
commit e497421d7f ("feat(versal): add infrastructure to handle
multiple interrupts") and commit 0654ab7f75 ("feat(versal-net): add
support for platform management").
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I07aa388d38ac3ff3c0d25decbe0719087b27ee18
Fix buffer calculation logic for Versal and Versal NET to use
LOCAL/REMOTE_ID.
Change-Id: Icf6985a19183cc8e51f3a536130695e00c32c736
Signed-off-by: Michal Simek <michal.simek@amd.com>
Use new macros IPI_LOCAL_ID/IPI_REMOTE_ID to specify source and
destination channels.
Change-Id: I558eebb4d4a83ae0ca9316824f9dba7426adbe3f
Signed-off-by: Michal Simek <michal.simek@amd.com>
This is preparation for cleaning up IPI local and remote side
communication. As of today macros are aligned to communication
channel but there is missing calculation based on channel
selection.
Change-Id: Iac7daf832ff372ea2fece72a15afdfe988b4b7db
Signed-off-by: Michal Simek <michal.simek@amd.com>
apu_ipi structure is not used anywhere externally that's why make it
static.
Change-Id: Icfa99e16ae36fcbcc83b0891aa3527993d49c7ed
Signed-off-by: Michal Simek <michal.simek@amd.com>
There is no need to include all headers. Enough to have only needed one.
Change-Id: I4813156404969df36f66c1102cd627fdc1e3e9dc
Signed-off-by: Michal Simek <michal.simek@amd.com>
The reason is to have all IPI related macros in the same file.
Change-Id: I88ddaa3a5dd1f10114371fc5405f8daf148ca3b8
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.
Change-Id: I14dee4729f88c407bafdf1d6b46106459d8e22c4
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Use the same format in all files 's/Copyright (C)/Copyright (c)/g'.
Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7
Signed-off-by: Michal Simek <michal.simek@amd.com>
There is missing comma in copyright line. It is better to have all
Copyrights align to the same style that's why fix it.
Change-Id: Ifc04b474e1a172a7243b073d944007cf17d76e87
Signed-off-by: Michal Simek <michal.simek@amd.com>
Remove unused PLAT_NUM_POWER_DOMAINS macro. Macro is referenced by
docs/design/psci-pd-tree.rst but it is not used in any calculation
that's why it is better to remove it.
Change-Id: I33f26cda6a4404061af5598ea4c751f64127e50a
Signed-off-by: Michal Simek <michal.simek@amd.com>
Switch to v2 version to add support for dynamic mapping which is not
supported in v1. It can be used for run time DT mapping.
Change-Id: I3f27591caf944dc758cc45ee870b9b5b3ff0a18d
Signed-off-by: Michal Simek <michal.simek@amd.com>
The commit a6f340fe58 ("Introduce the new BL handover interface")
extended handoff to 4 registers instead of 2. Arguments arg0-3 are
not used by platform code but in future they can be used for it.
But it doesn't make sense to checking their unused value.
Change-Id: I151e4b1574465409424453c054d937487086b79a
Signed-off-by: Michal Simek <michal.simek@amd.com>
The commit 6bb49c876c ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.
Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>
Replace FPD_MAINCCI* macros by PLAT_ARM_CCI* not to have two different
names for the same IP.
Change-Id: Ia1930e150a51603471051acec5c79c649d57f92f
Signed-off-by: Michal Simek <michal.simek@amd.com>
