Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.
Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Enable the MMU and add two entries to map the BL31 code and data
regions. Additional mappings will be added dynamically, enhancing
flexibility and modularity during the porting process.
Change-Id: I333c34c58274a115f62f54730bba5b71165e3e36
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Dynamically add entries for the GIC distributor and all its
redistributors for the cases when the platform is booted using enabled
MMU.
Change-Id: Ia810ec2329993057173e8fc25620a3df59b1e55d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Enable the MMU and add two entries to map the BL2 code and data regions.
Additional mappings will be added dynamically, enhancing flexibility and
modularity during the porting process.
Change-Id: I107abf944dfdce9dcff47b08272a5001484de8a9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Dynamically map the remaining regions part of the BL2 stages using
dynamic regions.
Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The regions used by the stages loaded by BL2 must be mapped before they
can be used.
Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.
Change-Id: Ib0dd2d0dbc9b4a574367141a7c96d76dd08e2c7f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the first core in isolation
to avoid crashes due to cache invalidation operations. Later,
it will disable the isolation and reconfigure the module every
time a new core is added or removed through PSCI.
Change-Id: Ida42db91b10be1e66c3b9b73674d1e37a61844dd
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
ERR051700 erratum applies to all S32G274A chip revisions; therefore,
it is enabled for the S32G274ARDB2 board.
Change-Id: I1ec436e99bc9328e42e74aef9d93f18e0f82bd7a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneously, may cause a false error in the fault control
unit.
The workaround is to clear the SRD resets sequentially instead of
simultaneously.
Change-Id: I883bc223bf6834907259e6964a5702d7186e4c7f
Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.
Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Implement a flush callback for the Linflex UART driver to avoid cases
where the BL31 stage reinitializes the console while there is ongoing TX
initiated by the BL2.
Change-Id: Ic49852f809198362de1f993474c7c45f1439dc98
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and Linflex clocks. For now, it will only contain the
frequency set for FXOSC. More clock management will be added in the next
commits.
Change-Id: Ie85465884de02f5082185f91749f190f40249c2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
To enable early clocks, such as A53, XBAR, and others, the clock driver
compilation should be included as part of the BL2 stage.
Change-Id: I17ba195d8c3cf3f91bd333a00d4a4af2f1f472b7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This corrects the following Coverity issue:
CID 425810: High impact quality (WRITE_CONST_FIELD).
A write to an aggregate overwrites a const-qualified field within the
aggregate.
(void)memset(&s32g2_console, 0, sizeof(s32g2_console));
Change-Id: Idc332be2c4dbf4858d2e9be0b41d5eba86587258
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, accelerators for automotive networking and many other
peripherals.
The added support is minimal and only includes the BL2 stage, with no
MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies
BL31 and BL33 from FIP to their designated addresses.
Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
