When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker
file aligns section on a page boundary. So having the -1 in
the size calculations leads to an error message looking like this:
bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte
While at it fix all other occurences of predefined values that were
calculated with -1.
Fixes: 1d333e6909 ("feat(versal-net): add support for Xilinx
Versal NET platform")
Change-Id: I4455f63ee3ad52369f517a7d8d3627faf0b28c0f
Signed-off-by: Michal Simek <michal.simek@amd.com>
This patch enables CTX_INCLUDE_PAUTH_REGS for RME builds.
The RMM-EL3 specification is also updated to reflect the changes
and also version of the same is bumped from 0.1 to 0.2.
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I2e96a592d2b75abaee24294240c1727c5ceba420
When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
aligns section on a page boundary. So having the -1 in the size
calculations leads to an error message looking like this:
bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte
While at it fix all other occurences of predefined values that were
calculated with -1
Fixes: commit f91c3cb1df ("arm64: versal: Add support for new Xilinx Versal ACAPs")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ica1f97867b701e7fcd60ea8ea07d2ae96c485443
When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
aligns section on a page boundary. So having the -1 in the size
calculations leads to an error message looking like this:
bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte
Commit 9b4ed0af02 ("feat(plat/zynqmp): fix section `coherent_ram' will not fit in region `RAM'")
applied a similar fix, but only in the predefined for BL31LIMIT/BASE.
While at it fix all other occurences of predefined values that were
calculated with -1
Fixes: 01555332fa ("zynqmp: Revise memory configuration options")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ic96e36808d01f6bb92e6839cec92fc52320dd3f3
This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I385455671413e154d04a879d33fdd774fcfefbd6
This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2f52d3eaf47716f7dfc636bbf1a23d68a04f39cb
Add checking on the size of source data does not exceed source size
when using memcpy and memset.
Add checking on the size of source data in FPGA Crypto Service does
not exceed the maximum of expected data size and does not meet the
minimum of expected data size.
Signed-off-by: Phui Kei Wong <phui.kei.wong@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Idb18f05c18d9142fbe703c3f4075341d179d8bad
Enable SEU ERR read interfaces for non-secure world to read out SEU status
for DDR.
SEU ERR SMC opcode updated to 0xC2000099
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I0618dfcdc86a7c1e0c8047b7214d369866dd2281
The feature support overview is meant to list all the major features
present in TF-A. It should be precise, non-exhaustive and up-to-date.
Updated the document with new features and removed few unnecessary
details.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I28b378f405a6b9d8f86e7b44e435c33625e3d260
Pin poetry to version 1.3.2, which is currently used in CI, to ensure
that all builds are consistent. Also, fix typo in `doc` group name.
Change-Id: Id0c1aa88ac7ffcc241a51c693570e87abacf7ebc
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Turning redistributor off during suspend disables any wakeup interrupts
resulting in cpu getting stuck. This patch removes the platform specific
psci pwr_domain_suspend handler.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I0a307cc140447e91fd0808fcfb309593f24c14ca
Turning redistributor off during suspend disables any wakeup interrupts
resulting in cpu getting stuck. This patch removes the platform specific
psci pwr_domain_suspend handler.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ic2ad5a561be29eee9229a5cc11aa3c9320a51cb7
Add results from running the TFTF test suite Runtime Instrumentation on Juno.
Change-Id: I4c5b64e1a80b5b88e42835f0700294a02edc8032
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
The commit 3e14df6f63 removed clearing of argument registers even when
BL31 is the first stage. In that case the registers are left in a random
state. TI platforms check that the arguments have been zero'd in early
setup and so all TI platforms are not broken. Not sure why this check was
here at all, so simply remove it to fix boot.
Fixes: 3e14df6f63 ("fix(bl31): avoid clearing of argument registers in RESET_TO_BL31 case")
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I02bdd16b67fb5facc4c47ec596a42f110a663377
Update to use the following software:
- mbed TLS == 3.4.0
- (DTC) >= 1.4.7
- Ubuntu 22.04 for builds.
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I384aab4dfee9cae9453eebf4091abe82ef9ccfaa
* changes:
test(tc): unify platform tests traces
test(tc): return test failures count for tfm-testsuite
test(tc): move platform tests in their own function
test(tc): centralize platform error handling
refactor(tc): define PLATFORM_TESTS for scale
Add some traces at the start and end of platform tests. These traces
are the same regardless of the set of platform tests we run (NV
counter tests / TF-M testsuite / future set of tests).
This makes it easier to integrate these tests in the CI because we can
now have a unified "expect" script for all platform tests, instead of
having one dedicated "expect" script for each possible set of tests.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I5ec30a7a25d8a9a4a90e3338a9789acff7ad4843
When running the "tfm-testsuite" set of platform tests, we now count
the number of failed tests (in addition to printing a test summary)
and report that back to the caller,
i.e. tc_bl31_common_platform_setup().
This will be useful to consolidate the tests failure reporting code in
a subsequent patch.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I8e51f03869f3b2f264b6581b3bd2a53be0198057
This is a bit cleaner, as it avoids cluttering the normal boot execution
path. It also gives us the opportunity to mark the tests function with
the __dead2 attribute, which inform both the compiler and the developer
that the test function never returns (since it suspends booting).
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I082a34a840ef791a2ac4c1f59b19b32aeb0a9ec7
Note that this change only affects the platform tests execution
path. It has no impact on the normal boot flow.
Make individual test functions propagate an error code, instead of
calling the platform error handler at the point of failure. The latter
is now the responsibility of the caller - in this case
tc_bl31_common_platform_setup().
Note that right now, tc_bl31_common_platform_setup() does not look at
the said error code but this initial change opens up an opportunity to
centralize any error handling in tc_bl31_common_platform_setup(),
which we will seize in subsequent patches.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ib282b64039e0b1ec6e6d29476fbaa2bcd33cb0c7
Per SMCCC documentation, bits [23:17] must be zero for Fast
SMCs. Other values are reserved for future use. Ensure that
these bits are zeroes for TEGRA_SIP_PMC_COMMANDS.
Commit f8a35797 introduced a check to return error if these
bits are not zero, thus breaking Tegra210 platforms. This
patch fixes the anomaly.
Change-Id: I19edc3b33c999a6fee6b86184233fba146316466
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Update the SPM threat model with information about FF-A v1.1
memory sharing functionality.
Change-Id: I65ea0d53aba8ac2f8432539968ceaab6be109ac8
Signed-off-by: J-Alves <joao.alves@arm.com>
Add documentation that explains implementation specific
relevant information from the update done to FF-A v1.1
memory sharing in Hafnium.
Change-Id: Ifc3c6b86c0545d53331207b017b990427ee84f2d
Signed-off-by: J-Alves <joao.alves@arm.com>
