From QEMU change:
> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
> and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
> In Armv8.6, the architecture standardized this frequency to 1GHz.
This change stops TF-A from hardcoding 62.5MHz frequency. Instead value
stored in CNTFRQ_EL0 would be used. As a result we get 62.5MHz on older
cores and 1GHz on newer ones.
Change-Id: I7d414ce6d3708e598bbb5a6f79eb2d4ec8e15ac4
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
As a part of removing DeviceTree from EDK2, we move functions to TF-A:
- counting the number of memory nodes
- checking NUMA node id
- checking the memory address
Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: Ib7bce3a65c817a5b3bef6c9e0a459c7ce76c7e35
Coverity Scan reminded that we need to take care of MPIDR properly.
We need to make sure that we get MPIDR values from QEMU.
No MPIDR == panic() in case which should not happen.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Idb5fe7d958f0bcecd3d66a643743f478538f4a8b
QEMU provides us with minimal information about hardware platform using
minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
a firmware DeviceTree.
Change-Id: I7b6cc5f53a4f78a9ed69bc7fc2fa1a69ea65428d
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
We want to remove use of DeviceTree from EDK2. So we move
functions to TF-A:
- counting cpu cores
- checking NUMA node id
- checking MPIDR
And then it gets passed to EDK2 via SMC calls.
Change-Id: I1c7fc234ba90ba32433b6e4aa2cf127f26da00fd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ibf9376caabbc05ceef4f870d816e6c60a344f895
RME patch series shown that we can build larger BL1 than we can run:
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOTICE: BL1: Built : 12:10:39, Sep 18 2023
INFO: BL1: RAM 0x3ffee000 - 0x3fffb000
INFO: BL1: Loading BL2
WARNING: Firmware Image Package header check failed.
RME pushed debug build BL1 over 0x8000 in size.
This exposed an error where FIP_BASE (supposed to be at BL1_SIZE offset
from start of flash) was actually 0x8000 and not 0x12000.
Make sure we have space for BL1 by deriving FIP_BASE from it.
Note: this is a breaking change for edk2 FD image generation, which had
similarly hardcoded a 0x8000 offset. These images must be updated in
lock-step.
Change-Id: I8a1a85e82319945a4412c424467d818d5b6e4ecd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
references in platform.mk files and also in one rst which is not valid
anymore.
Change-Id: I45f8e7db0a14ce63de62509100d8159b7aca2657
Signed-off-by: Michal Simek <michal.simek@amd.com>
There are some variables to enable/disable options. Let keep them at top
of file.
Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:
> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14: *** "Error: SPM_MM is not compatible with ENABLE_SVE_FOR_NS". Stop.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Iabe181647fce00a432ae11dc4599b71619364c24
Handle coherency in one place for AArch64 mode.
Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Enable SVE, SME, RNG, FGT in one place.
qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I2e8f971ef3e42d9ebe9f20641b288cc8c40f806a
Move BL31 source list into common file.
Change-Id: Iaa27cfd8f87b691728379c87a6ff6331e87951e1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Move BL1 and BL2 source list into common file.
Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not matter.
Change-Id: I5b8f7d18dc903e86e0cc7babbc2fb3f26a1bfdfa
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Move libfdt includes into common file and use definitions from them.
Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Add support to qemu "neoverse-v1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.
Change-Id: Id710e2b960e7938d2dbe7a88d9e158a7009fc3d1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Read data from DeviceTree provided by QEMU, provide via SMC
to the next firmware level.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I95c5f00ab2cca3b5fda122dcc8d7704a7a82059b
QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I383919bd172acc8873292a0c5e4469651dc96fb9
QEMU provides platform version information via DT. We want to use it
in firmware to handle differences between platform versions.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I8def66dac9dd5d7ab0e459baa40e27a11b65f0ba
QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.
So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238
Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS ( for fixed/real platforms)
2: FEAT_STATE_CHECK ( for configurable platforms)
to meet the feature detection requirements dynamically, mainly
targetting configurable/Fixed Virtual platforms.
With this mechanism in place, we are refactoring all the existing
feature flags to the FEAT_STATE_CHECK option(=2), including
FEAT_SVE explicitly for FVPs.
SVE Patch Reference:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19888/25
This newly introduced change, breaks the existing behaviour especially
for virtual platforms, who have set the ENABLE_SVE_FOR_NS flag to 1.
Moving ahead, we advise the platforms to take the following steps while
enabling the features:
1. If the platform is configurable (virtual), and want to ensure feature
detection happens dynamically at runtime, set the build flags to
FEAT_STATE_CHECK(=2).
2. For real(fixed) platforms, depending on the features supported by the
hardware and platform wants to enable it, platforms could set build
flags to FEAT_STATE_ALWAYS(=1).
(Note: Only the non-secure world enablement related build flags have
been refactored to take the values within 0 to 2. As earlier Secure
world enablement flags will still remain boolean.)
Henceforth, in order to keep it aligned with this tri-state mechanism,
changing the qemu platform default to the now supported dynamic
option(=2), so the right decision can be made by the code at runtime.
Change-Id: Icc95b8b872378b7874d4345b631adfc314e4dada
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c71115451ae91a1643812d89ec7c071f
Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.
This change introduces the period prefix to all specialized section
names.
BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.
Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>
Commit 337ff4f1dd enabled SVE/SME for
qemu platform. Let do the same for qemu-sbsa one too.
With this change I can boot Debian 'bookworm' installed using Max cpu.
Info from referenced commit:
Starting with QEMU v3.1.0 (Dec 2018), QEMU's TCG emulation engine supports
the SVE architecture extension. In QEMU v7.1.0 (Aug 2022) it also gained
SME support.
As it stands today, running TF-A under QEMU with "-cpu max" makes Linux
hang, because SME and SVE accesses trap to EL3, but are never handled
there. This is because the Linux kernel sees the SVE or SME feature bits,
and assumes firmware has enabled the feature for lower exception levels.
This requirement is described in the Linux kernel booting protocol.
Enable those features in the TF-A build, so that BL31 does the proper
EL3 setup to make the feature usable in non-secure world.
We check the actual feature bits before accessing SVE or SME registers,
so this is safe even for older QEMU version or when not running with
-cpu max. As SVE and SME are AArch64 features only, do not enable them
when building for AArch32.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I9ea1f91e6b801218d944e8a7d798d5ae568ed59a
This has been introduced to simplify dependencies on the FDT wrappers.
We generally want to avoid pulling in components on a file-by-file
basis, particularly as we are trying to draw conceptual boxes around
components in preparation for transitioning the build system to CMake,
where dependencies are modelled on libraries rather than files.
Signed-off-by: Chris Kay <chris.kay@arm.com>
Change-Id: Idb7ee05a9b54a8caa3e07f36e608867e20b6dcd5
Add support to qemu "max" cpu for both "qemu" ('virt') and
"qemu_sbsa" ('sbsa-ref') platforms.
Change-Id: I36e45c0a3c4e30ba546d2a3cb44dfef11a680305
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
This commit fixes the wrong memory type, secure NOR flash
shall be mapped as MT_DEVICE.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I9c9ed51675d84ded675bb56b2e4ec7a08184c602
sbsa-ref in QEMU may create up to 512 cores.
This commit prepares the MP information to support 512 cores.
The number of xlat tables for spm_mm is also increased.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I2788eaf6d14e188e9b5d1102d359b2899e02df7c
This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.
This required a sbsa-ref specific version of PSCI functions for the
platform. Also adjusted the MMU range to also include the new EC.
Add a new MMU region for the embedded controller and increase the
size of xlat tables by one for the new region.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee
sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512
cores in upto 64 clusters. Implement a qemu_sbsa specific topology file
and increase the BL31_SIZE to accommodate the bigger table sizes. Change
platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so
plat_helpers.S calculates correct result.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7
Rather than re-create this file in multiple qemu variants instead
caclulate the shift needed to convert MPIDR to position.
Add a new PLATFORM_CPU_PER_CLUSTER_SHIFT define in platform_def.h
for both qemu and qemu_sbsa to enable this calculation.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I0e3a86354aa716d95150a3a34b15287cd70c8fd2
This implements support for UEFI secure variable storage
using standalone MM framework on qemu_sbsa platform.
Non-secure shared memory between UEFI and standalone MM
is allocated at the top of DRAM.
DRAM size of qemu_sbsa varies depends on the QEMU parameter,
so the non-secure shared memory is allocated by trusted firmware
and passed the base address and size to UEFI through device tree
"/reserved-memory" node.
Change-Id: I367191f408eb9850b7ec7761ee346b014c539767
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Increase SHARED_RAM_SIZE in sbsa_qemu platform from 4KB to 8KB.
sbsa_qemu uses SHARED_RAM for mail box and hold state of each cpus. If
qemu is configured with 512 cpus, region size used by qemu is greater
than 4KB.
Signed-off-by: Masato Fukumori <masato.fukumori@linaro.org>
Change-Id: I639e44e89335249d385cdc339350f509e9bd5e36
Include libraries needed to emulate Cortex-A72 on
sbsa-ref target of QEMU.
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Change-Id: I98cf17b1662c70898977a841af07e07b5cfca8ba
The qemu_sbsa platform uses 42bit address size but
the cortex-a53 only supports 40bit addressing, the
cpu is incompatible with the platform.
The aem_generic is also not used with qemu_sbsa, in
fact, the platform currently only properly supports
the cortex-a57 cpu.
Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14
Signed-off-by: Tomas Pilar <tomas@nuviateam.com>
Enable the spm_mm framework for the qemu_sbsa platform.
Memory layout required for spm_mm is created in secure SRAM.
Co-developed-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
64KB was not enouth to handle fdt, bl2 shows
following error message.
"ERROR: Invalid Device Tree at 0x10000000000: error -3"
This patch increases the size to 1MB to address above error.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I0726a0cea95087175451da0dba7410acd27df808
This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.
The patch adds GICv3 driver configuration flags
'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and
'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in
'GICv3 driver options' section of 'build-option.rst'
document.
NOTE: Platforms with GICv3 driver need to be modified to
include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles.
Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3.1 and GICv4 support.
NOTE: Platforms need to modify to include both
'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the
single helper file previously.
Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.
Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03
This lets the Linux kernel or any other image which expects an FDT in x0 be
loaded directly as BL33 without a separate bootloader on QEMU.
Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: Ia8eb4710a3d97cdd877af3b8aae36a2de7cfc654
This patch adds mapping for secure FLASH0 for qemu/virt and
qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both
platforms share common code, changes in common defines was necessary.
For qemu_sbsa, this patch adds necessary mapping in order to boot without
semi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with
variables) since it need to "run in place" in non secure domain. Changes
for this are under RFC at edk2-platforms mailing list:
https://patches.linaro.org/patch/171327/
(edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc).
In docs qemu/virt is described as using semi-hosting, therefore this change
should be orthogonal to existing assumptions while giving possibility to
store both bl1 and fip in FLASH0 at some point (additional changes required
for that).
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28
This patch introduces Qemu SBSA platform.
Both platform specific files where copied from qemu/qemu with changes for
DRAM base above 32bit and removal of ARMv7 conditional defines/code.
Documentation is aligned to rest of SBSA patches along the series and
planed changes in edk2-platform repo.
FixesARM-software/tf-issues#602
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I8ebc34eedb2268365e479ef05654b2df1b99128c
