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refactor(qemu): do not hardcode counter frequency
From QEMU change: > In previous versions of the Arm architecture, the frequency of the > generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value, > and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns. > In Armv8.6, the architecture standardized this frequency to 1GHz. This change stops TF-A from hardcoding 62.5MHz frequency. Instead value stored in CNTFRQ_EL0 would be used. As a result we get 62.5MHz on older cores and 1GHz on newer ones. Change-Id: I7d414ce6d3708e598bbb5a6f79eb2d4ec8e15ac4 Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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c8be7c08c3
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3 changed files with 1 additions and 11 deletions
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@ -161,7 +161,7 @@ void bl31_platform_setup(void)
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unsigned int plat_get_syscnt_freq2(void)
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{
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return SYS_COUNTER_FREQ_IN_TICKS;
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return read_cntfrq_el0();
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}
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/*******************************************************************************
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@ -301,11 +301,6 @@
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#define PLAT_SDEI_NORMAL_PRI 0x70
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#define PLAT_SDEI_SGI_PRIVATE QEMU_IRQ_SEC_SGI_0
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/*
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* System counter
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*/
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#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
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/*
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* Maximum size of Event Log buffer used in Measured Boot Event Log driver
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*/
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@ -266,11 +266,6 @@
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#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE
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#define PLAT_QEMU_DT_MAX_SIZE 0x100000
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/*
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* System counter
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*/
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#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
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#if SPM_MM
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#define PLAT_QEMU_SP_IMAGE_BASE BL_RAM_BASE
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#define PLAT_QEMU_SP_IMAGE_SIZE ULL(0x300000)
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