This patch adds some documentation for the context management library.
It mainly covers the design at a higher level, with more focus on
the cold boot and warm boot entries as well as the operations
involved during context switch. Further it also includes a section
on feature enablement for individual world contexts.
Change-Id: I77005730f4df7f183f56a2c6dd04f6362e813c07
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Currently we are building vendor-specific EL3 by default similar to
arm-sip but unfortunately this causes few troubles for now.
- Few model builds configuration like 'fvp-dynamiq-aarch64-only'
is on 256KB SRAM border and this configuration is also run on some
older models like A710 and N2, so we cant move them to 384KB SRAM size
and to new model.
- Not able to move some older model builds to new model due to known
issue in power modelling in some of the models, making it difficult to
transition.
However vendor-specific EL3 is currently using PMF, DEBUGFS so building
the vendor EL3 support only when any of this sub-service is built also
helps to avoid bloating BL31 image size in certain configurations.
However this is not end of road, we will monitor how vendor-specific EL3
grows with sub-service and if needed will make this interface to built
by default like arm-sip range. Also this doesn't stop platform owners to
make vendor-specific EL3 to be enabled by default for their platform
configuration.
Change-Id: I23322574bdeb7179441a580ad4f093216a948bbf
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
With addition of vendor-specific el3 monitor service calls debugfs and
pmf are moved from arm-sip to vendor-specific el3 range.
Going forward any changes to SMCCC services can be captured from docs
file table.
Use one FID allocated per sub-feature to track changes in sub-feature.
Modify top level version only when we break version probing or
discovery.
Change-Id: I14ceeab79f29ae57a5d7c523147f6ecaa5574f79
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documentation 1.5:
https://developer.arm.com/documentation/den0028/latest
Add a deprecation notice to inform PMF is moved from arm-sip range to
vendor-specific EL3 range. PMF support from arm-sip range will be
removed and will not available after TF-A 2.12 release.
Change-Id: Ie1e14aa601d4fc3db352cd5621d842017a18e9ec
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Move debugfs to Vendor-Specific EL3 Monitor Service Calls.
Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and
allocated subranges of Function identifiers to different services are:
0x87000000-0x8700FFFF-SMC32: Vendor-Specific EL3 Monitor Service Calls
0xC7000000-0xC700FFFF-SMC64: Vendor-Specific EL3 Monitor Service Calls
Amend Debugfs FID's to use this range and id.
Add a deprecation notice to inform debugfs moved from arm-sip range to
Vendor-Specific EL3 range. Debugfs support from arm-sip range will be
removed and will not be available after TF-A 2.12 release.
Reference to debugfs component level documentation:
https://trustedfirmware-a.readthedocs.io/en/latest/components/debugfs-design.html#overview
Change-Id: I97a50170178f361f70c95ed0049bc4e278de59d7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Add support for vendor-specific el3 service. SMCCC 1.5 introduces
support for vendor-specific EL3 monitor calls.
SMCCC Documentation reference:
https://developer.arm.com/docs/den0028/latest
Change-Id: Id8bc43842eecdb7a8a2ec7f31a631e88fe4fe0b4
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Add vendor specific el3 function id and update docs for the same.
SMCCC Documentation reference:
https://developer.arm.com/documentation/den0028/latest
Change-Id: Ieeb63608ad74d7b764d7131d8a92ecf10053c50d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Move CPUs which are not tested in CI under a new build option.
We have added some CPUs for which there is no FVP models available
yet to test. Move those CPUs under a new FVP build option.
Change-Id: I3da12d2f8d9c246b435b31adfac61c79dc1ab0cb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Replace "adr" with "adr_l" to handle symbols or labels that exceeds 1MB
access range. This modification resolves the link error.
Change-Id: I9eba2e34c0a303b40e4c7b3ea7c5b113f4c6d989
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Introduce the macro "adr_l," which can handle symbols or labels that
exceed the 1MB access range compared to the "adr" instruction.
Change-Id: Iab2a2a2f8a11a5e21e386f1001ba27a8de621132
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
The newly introduced wrapper macro CREATE_FEATURE_PRESENT
replaces the read_feat_xx_id_field function that returns
an integer with the is_feat_xx_present function that returns
a boolean based on the idfield, mask and feature enablement flag.
This impacts check_feature api which is explicilty used in
detect_arch_features procedure. In order to keep it in original
form, the read functions have been added. Further, the scope has
also been reduced to static without introducing any additonal
overhead on code size, as the feat_detect.c is included for build
only when the FEATURE_DETECTION flag is enabled.
Change-Id: If364f32837a2ad19f49e4f0d355274bf7f26aaac
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all the features:
-> is_feat_xx_present(): Does Hardware implement the feature.
-> uniformity in naming the function across multiple features.
-> improved readability
The is_feat_xx_present() is implemented to check if the hardware
implements the feature and does not take into account the
ENABLE_FEAT_XXX flag enabled/disabled in software.
- CREATE_FEATURE_PRESENT(name, idreg, shift, mask, idval)
The wrapper macro reduces the function to a single line and
creates the is_feat_xx_present function that checks the
id register based on the shift and mask values and compares
this against a determined idvalue.
Change-Id: I7b91d2c9c6fbe55f94c693aa1b2c50be54fb9ecc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Currently, the macros used to denote feature implementation
in hardware follow a random pattern with a few macros having
suffix as SUPPORTED and a few using the suffix IMPLEMENTED.
This patch aligns the macro names uniformly using the suffix
IMPLEMENTED across all the features and removes unused macros
pertaining to the Enable feat mechanism.
FEAT_SUPPORTED --> FEAT_IMPLEMENTED
FEAT_NOT_SUPPORTED --> FEAT_NOT_IMPLEMENTED
Change-Id: I61bb7d154b23f677b80756a4b6a81f74b10cd24f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
The pm_get_proc_by_node() is not used anywhere. Hence remove the
same.
Change-Id: Ifd68dd524cae0a9f1684d943019563027859ccea
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
commit@138221c2457b9d04101b84084c07d576b0eb5a51 reduced items that
should be build due to SRAM size limitations.
But newer models from 11.19 onwards support to set SRAM size greater
than 256KB. So remove all dependency and conditional builds for FVP.
Change-Id: I38684e100450b74fdda0d685775e2cbce92170b6
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Commit c282384db ("refactor(mte): remove mte, mte_perm") removes the
option FEAT_MTE and introduces FEAT_MTE2 option. Afterwards, the
FEAT_MTE2 option is missed on the TC platform and the feature is
disabled. As a result, it causes the panic in secure world.
This patch enables the FEAT_MTE2 option for TC platform to allow the
secure world can access the MTE registers properly.
Change-Id: If697236aa59bf4fb374e0ff43b53455ac2154e9c
Fixes: c282384db ("refactor(mte): remove mte, mte_perm")
Signed-off-by: Leo Yan <leo.yan@arm.com>
It is expected that kernel can control the flow of the TF-A operations.
This patch remove the apusys kernel handler usage constraints, making
the operations all controlled on kernel side.
Signed-off-by: Karl Li <karl.li@mediatek.com>
Change-Id: Idc205a2cf23e1ff5f1920658a3b089c823f0288a
The stack is too small for VERBOSE logging when secure world is disabled
as there is a recursive call when printing the translation table state
which causes a crash.
Changing the stack to the same value regardless of trusted boot.
Change-Id: I12298b33e47ae5206f74370262edce06b8a75d99
Signed-off-by: Alex Dobrescu <alex.dobrescu@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'
When BL2 is enabled as the entrypoint in the reset vector, none of the
TL initialisation ordinarily performed in BL1 will have been done. This
change ensures that BL2 has a secure TL to pass information onto BL31
through.
Change-Id: I553b0b7aac9390cd6a2d63471b81ddc72cc40a60
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Leverage the framework between BL1 and BL2. Migrate all handoff
structures to the TL.
Change-Id: I79ff3a319596b5656184cde10b5204b10a4d03bb
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
`TL_TAG_RW_MEM_LAYOUT64` encapsulates a structure used to represent the
layout of a region of memory on 64-bit platforms [2]. In TF-A this is
used to represent the `meminfo_t` structure passed between BL1 and BL2,
which provides BL2 with information about the space it has available in
BL2. The `TL_TAG_TB_FW_CONFIG` entry type encapsulates the trusted
bootloader firmware configuration [1].
[1] https://github.com/FirmwareHandoff/firmware_handoff/pull/37
[2] https://github.com/FirmwareHandoff/firmware_handoff/pull/36
Change-Id: I1e0eeec2ec204e469896490d42a9dce9b1b2f209
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Layout calculation is spread out between core BL1 logic and common
platform code. Relocate these into common platform code so they are
organised logically.
Change-Id: I8b05403e41b800957a0367316cecd373d10bb1a4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Add support for the firmware handoff framework between BL2 and BL31.
Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes
in recent models. Load the HW_CONFIG as a TE along with entry point
parameters for BL31 execution.
Change-Id: I7c4c6e8353ca978a13520fb3e15fb2803f0f1d0e
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
* changes:
feat(docs): update maintainer list for neoverse_rd
refactor(neoverse-rd): remove soc_css.mk from common makefile
refactor(neoverse-rd): unify GIC SPI range macros
refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file
feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms
feat(rdn2): enable AMU if present on the platform
feat(rdn2): enable MTE2 if present on the platform
refactor(neoverse-rd): move defines out of platform_def.h
refactor(neoverse-rd): add defines for ROM, SRAM and DRAM2
refactor(neoverse-rd): define naming convention for RoS macros
refactor(neoverse-rd): define naming convention for CSS macros
refactor(neoverse-rd): refactor mmap macro for RoS device memory region
refactor(neoverse-rd): refactor mmap macro for CSS device memory region
refactor(neoverse-rd): set mmap naming convention
refactor(neoverse-rd): rename nrd_plat_v2.c to align with convention
refactor(neoverse-rd): refactor nrd_soc_css_def_v2.h file
refactor(neoverse-rd): refactor nrd_soc_platform_def_v2.h file
refactor(neoverse-rd): refactor nrd_base_platform_def.h
refactor(neoverse-rd): header files for second generation platforms
Add Rohit.Mathew@arm.com to the maintainer list for Neoverse Reference
Design platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1b8a5714e2707162dd973d9a50215d0a6b622eb1
The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 within the
SOC specification. However, as none of the Neoverse reference design
platforms necessitate the initialization of PCIe or NIC400, remove the
soc_css.mk from the common makefile.
Additionally, empty initialization functions for PCIe and NIC400 are
added to satisfy the requirements of the plat/arm common code, which
expects these functions to be present.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia431af62f48fc224962d64902dd3acfbf0b93935
The existing macros representing GIC SPI minimum and maximum for
multichip platforms lack a consistent naming convention. To address
this, establish the convention "NRD_CHIP<x>_SPI_MIN" and
"NRD_CHIP<x>_SPI_MAX" for use across all Neoverse Reference Design
multichip platforms.
Furthermore, extend this naming convention to RD-N2-Cfg2 and introduce
similar macros.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idca2a8c66579f05e712e3b6e95204fedc122cf23
Consolidate and organize platform port definitions within the
nrd_plat_arm_def2.h file. Remove direct references to addresses with
corresponding RoS or CSS definitions.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic43cff90d2cf45760b3f808732754cf7c05a814a
SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value to 0.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib503c5552e2b8fee928b2392ba40805664d857d7
Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could access system registers relevant to AMU without causing a trap to
EL3.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic9aa435af54eddacdaa49e69f25893ddaa977e3e
MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
could potentially access the featre registers leading EL3 traps.
Therefore, set MTE2 build option to '2' to enable the feature only if
its implemented on the platform.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I97c341ac38485937eb18ce9bdcffec26c0e5e76d
